This is a note to let you know that I've just added the patch titled
arm64: dts: qcom: sm8350: switch UFS QMP PHY to new style of bindings
to the 6.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-dts-qcom-sm8350-switch-ufs-qmp-phy-to-new-styl.patch
and it can be found in the queue-6.7 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit 880369e216f961cf020da91da9585f428eff3391
Author: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Date: Tue Dec 5 06:25:51 2023 +0300
arm64: dts: qcom: sm8350: switch UFS QMP PHY to new style of bindings
[ Upstream commit 002a13ed10136e4f59013adbf097b31d608caf67 ]
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20231205032552.1583336-9-dmitry.baryshkov@xxxxxxxxxx
Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
Stable-dep-of: 8edbdefee1c9 ("arm64: dts: qcom: sm8350: Fix UFS PHY clocks")
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a72f3c470089b..19172ed7ec2be 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -677,9 +677,9 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
- <&ufs_mem_phy_lanes 0>,
- <&ufs_mem_phy_lanes 1>,
- <&ufs_mem_phy_lanes 2>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<0>;
};
@@ -1679,7 +1679,7 @@ ufs_mem_hc: ufshc@1d84000 {
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -1723,10 +1723,8 @@ ufs_mem_hc: ufshc@1d84000 {
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8350-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
@@ -1734,17 +1732,11 @@ ufs_mem_phy: phy@1d87000 {
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x188>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x188>,
- <0 0x01d87a00 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
};
cryptobam: dma-controller@1dc4000 {
