On 05/03/2024 08:49, Greg KH wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Tue, Mar 05, 2024 at 08:05:30AM +0000, Conor.Dooley@xxxxxxxxxxxxx wrote: >> On 05/03/2024 07:44, gregkh@xxxxxxxxxxxxxxxxxxx wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> This is a note to let you know that I've just added the patch titled >>> >>> riscv: Add a custom ISA extension for the [ms]envcfg CSR >>> >>> to the 6.7-stable tree which can be found at: >>> http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary >>> >>> The filename of the patch is: >>> riscv-add-a-custom-isa-extension-for-the-envcfg-csr.patch >>> and it can be found in the queue-6.7 subdirectory. >>> >>> If you, or anyone else, feels it should not be added to the stable tree, >>> please let <stable@xxxxxxxxxxxxxxx> know about it. >>> >>> >>> From 4774848fef6041716a4883217eb75f6b10eb183b Mon Sep 17 00:00:00 2001 >>> From: Samuel Holland <samuel.holland@xxxxxxxxxx> >>> Date: Tue, 27 Feb 2024 22:55:34 -0800 >>> Subject: riscv: Add a custom ISA extension for the [ms]envcfg CSR >>> >>> From: Samuel Holland <samuel.holland@xxxxxxxxxx> >>> >>> commit 4774848fef6041716a4883217eb75f6b10eb183b upstream. >>> >>> The [ms]envcfg CSR was added in version 1.12 of the RISC-V privileged >>> ISA (aka S[ms]1p12). However, bits in this CSR are defined by several >>> other extensions which may be implemented separately from any particular >>> version of the privileged ISA (for example, some unrelated errata may >>> prevent an implementation from claiming conformance with Ss1p12). As a >>> result, Linux cannot simply use the privileged ISA version to determine >>> if the CSR is present. It must also check if any of these other >>> extensions are implemented. It also cannot probe the existence of the >>> CSR at runtime, because Linux does not require Sstrict, so (in the >>> absence of additional information) it cannot know if a CSR at that >>> address is [ms]envcfg or part of some non-conforming vendor extension. >>> >>> Since there are several standard extensions that imply the existence of >>> the [ms]envcfg CSR, it becomes unwieldy to check for all of them >>> wherever the CSR is accessed. Instead, define a custom Xlinuxenvcfg ISA >>> extension bit that is implied by the other extensions and denotes that >>> the CSR exists as defined in the privileged ISA, containing at least one >>> of the fields common between menvcfg and senvcfg. >>> >>> This extension does not need to be parsed from the devicetree or ISA >>> string because it can only be implemented as a subset of some other >>> standard extension. >>> >>> Cc: <stable@xxxxxxxxxxxxxxx> # v6.7+ >>> Signed-off-by: Samuel Holland <samuel.holland@xxxxxxxxxx> >>> Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> >>> Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx> >>> Link: https://lore.kernel.org/r/20240228065559.3434837-3-samuel.holland@xxxxxxxxxx >>> Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> >>> Cc: Ron Economos <re@xxxxxxxx> >>> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> >>> --- >>> arch/riscv/include/asm/hwcap.h | 2 ++ >>> arch/riscv/kernel/cpufeature.c | 14 ++++++++++++-- >>> 2 files changed, 14 insertions(+), 2 deletions(-) >>> >>> --- a/arch/riscv/include/asm/hwcap.h >>> +++ b/arch/riscv/include/asm/hwcap.h >>> @@ -58,6 +58,8 @@ >>> #define RISCV_ISA_EXT_SMSTATEEN 43 >>> #define RISCV_ISA_EXT_ZICOND 44 >>> >>> +#define RISCV_ISA_EXT_XLINUXENVCFG 127 >>> + >>> #define RISCV_ISA_EXT_MAX 64 >> >> These defines here need to be lower than RISCV_ISA_EXT_MAX. >> I think adjusting the value of XLINUXENVCFG to 63 will >> suffice here, the max got bumped to 128 in 6.8. > > Ok, then why was this tagged for stable inclusion as-is? I dunno, I just reviewed the patch for mainline :) I did see a rejection email originally for this patch, so I was expecting to see a manual backport from Samuel for it. > Can you propose a fixed change instead? I'd just squash in the following, so that it uses a valid id: diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 1b7f362713db..aa65ac8624a8 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -58,7 +58,7 @@ #define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_ZICOND 44 -#define RISCV_ISA_EXT_XLINUXENVCFG 127 +#define RISCV_ISA_EXT_XLINUXENVCFG 63 #define RISCV_ISA_EXT_MAX 64
