Patch "drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz" has been added to the 6.1-stable tree

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



This is a note to let you know that I've just added the patch titled

    drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-increased-min_dcfclk_mhz-and-min_fcl.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 09aee12b42f5c10e4b3f96893af38ee76ae2b125
Author: Sohaib Nadeem <sohaib.nadeem@xxxxxxx>
Date:   Tue Jan 16 11:00:00 2024 -0500

    drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz
    
    [ Upstream commit 2ff33c759a4247c84ec0b7815f1f223e155ba82a ]
    
    [why]
    Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased
    to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware
    requirement will still be satisfied. Increasing min DCFCLK addresses
    underflow issues (underflow occurs when phantom pipe is turned on for some
    Sub-Viewport configs).
    
    [how]
    Increasing DCFCLK by raising the min_dcfclk_mhz
    
    Reviewed-by: Chaitanya Dhere <chaitanya.dhere@xxxxxxx>
    Reviewed-by: Alvin Lee <alvin.lee2@xxxxxxx>
    Acked-by: Tom Chung <chiahsuan.chung@xxxxxxx>
    Signed-off-by: Sohaib Nadeem <sohaib.nadeem@xxxxxxx>
    Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 85e0d1c2a9085..baecc0ffe7580 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2123,7 +2123,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
 	unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
 			max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
 
-	unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
+	unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599;
 
 	static const unsigned int num_dcfclk_stas = 5;
 	unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};




[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Index of Archives]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux