Patch "i2c: qcom-geni: Correct I2C TRE sequence" has been added to the 6.6-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    i2c: qcom-geni: Correct I2C TRE sequence

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     i2c-qcom-geni-correct-i2c-tre-sequence.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit ac678bba0ce75d9e0a6d0fc263aa784949461bde
Author: Viken Dadhaniya <quic_vdadhani@xxxxxxxxxxx>
Date:   Mon Feb 12 18:22:39 2024 +0530

    i2c: qcom-geni: Correct I2C TRE sequence
    
    [ Upstream commit 83ef106fa732aea8558253641cd98e8a895604d7 ]
    
    For i2c read operation in GSI mode, we are getting timeout
    due to malformed TRE basically incorrect TRE sequence
    in gpi(drivers/dma/qcom/gpi.c) driver.
    
    I2C driver has geni_i2c_gpi(I2C_WRITE) function which generates GO TRE and
    geni_i2c_gpi(I2C_READ)generates DMA TRE. Hence to generate GO TRE before
    DMA TRE, we should move geni_i2c_gpi(I2C_WRITE) before
    geni_i2c_gpi(I2C_READ) inside the I2C GSI mode transfer function
    i.e. geni_i2c_gpi_xfer().
    
    TRE stands for Transfer Ring Element - which is basically an element with
    size of 4 words. It contains all information like slave address,
    clk divider, dma address value data size etc).
    
    Mainly we have 3 TREs(Config, GO and DMA tre).
    - CONFIG TRE : consists of internal register configuration which is
                   required before start of the transfer.
    - DMA TRE :    contains DDR/Memory address, called as DMA descriptor.
    - GO TRE :     contains Transfer directions, slave ID, Delay flags, Length
                   of the transfer.
    
    I2c driver calls GPI driver API to config each TRE depending on the
    protocol.
    
    For read operation tre sequence will be as below which is not aligned
    to hardware programming guide.
    
    - CONFIG tre
    - DMA tre
    - GO tre
    
    As per Qualcomm's internal Hardware Programming Guide, we should configure
    TREs in below sequence for any RX only transfer.
    
    - CONFIG tre
    - GO tre
    - DMA tre
    
    Fixes: d8703554f4de ("i2c: qcom-geni: Add support for GPI DMA")
    Reviewed-by: Andi Shyti <andi.shyti@xxxxxxxxxx>
    Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
    Tested-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx> # qrb5165-rb5
    Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@xxxxxxxxxxx>
    Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@xxxxxxxxxxx>
    Signed-off-by: Viken Dadhaniya <quic_vdadhani@xxxxxxxxxxx>
    Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
    Signed-off-by: Andi Shyti <andi.shyti@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 0a9d389df301..5cc32a465f12 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -613,20 +613,20 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], i
 
 		peripheral.addr = msgs[i].addr;
 
+		ret =  geni_i2c_gpi(gi2c, &msgs[i], &config,
+				    &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c);
+		if (ret)
+			goto err;
+
 		if (msgs[i].flags & I2C_M_RD) {
 			ret =  geni_i2c_gpi(gi2c, &msgs[i], &config,
 					    &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c);
 			if (ret)
 				goto err;
-		}
-
-		ret =  geni_i2c_gpi(gi2c, &msgs[i], &config,
-				    &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c);
-		if (ret)
-			goto err;
 
-		if (msgs[i].flags & I2C_M_RD)
 			dma_async_issue_pending(gi2c->rx_c);
+		}
+
 		dma_async_issue_pending(gi2c->tx_c);
 
 		timeout = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);