This is a note to let you know that I've just added the patch titled
dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
to the 6.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
dt-bindings-timer-thead-c900-aclint-mtimer-separate-mtime-and-mtimecmp-regs.patch
and it can be found in the queue-6.7 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From b91cf01cf3e63a627b3b65f4284dcf9a4deb80f9 Mon Sep 17 00:00:00 2001
From: Inochi Amaoto <inochiama@xxxxxxxxxxx>
Date: Mon, 4 Dec 2023 17:51:08 +0800
Subject: dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
From: Inochi Amaoto <inochiama@xxxxxxxxxxx>
commit b91cf01cf3e63a627b3b65f4284dcf9a4deb80f9 upstream.
The timer registers of aclint don't follow the clint layout and can
be mapped on any different offset. As sg2042 uses separated timer
and mswi for its clint, it should follow the aclint spec and have
separated registers.
The previous patch introduced a new type of T-HEAD aclint timer which
has clint timer layout. Although it has the clint timer layout, it
should follow the aclint spec and uses the separated mtime and mtimecmp
regs. So a ABI change is needed to make the timer fit the aclint spec.
To make T-HEAD aclint timer more closer to the aclint spec, use
regs-names to represent the mtimecmp register, which can avoid hack
for unsupport mtime register of T-HEAD aclint timer.
Also, as T-HEAD aclint only supports mtimecmp, it is unnecessary to
implement the whole aclint spec. To make this binding T-HEAD specific,
only add reg-name for existed register. For details, see the discussion
in the last link.
Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxxxx>
Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Link: https://lore.kernel.org/all/IA1PR20MB4953F9D77FFC76A9D236922DBBB6A@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/
Acked-by: Guo Ren <guoren@xxxxxxxxxx>
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
Link: https://lore.kernel.org/r/IA1PR20MB49531ED1BCC00D6B265C2D10BB86A@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
.../bindings/timer/thead,c900-aclint-mtimer.yaml | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
index fbd235650e52..2e92bcdeb423 100644
--- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
+++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
@@ -17,7 +17,12 @@ properties:
- const: thead,c900-aclint-mtimer
reg:
- maxItems: 1
+ items:
+ - description: MTIMECMP Registers
+
+ reg-names:
+ items:
+ - const: mtimecmp
interrupts-extended:
minItems: 1
@@ -28,6 +33,7 @@ additionalProperties: false
required:
- compatible
- reg
+ - reg-names
- interrupts-extended
examples:
@@ -39,5 +45,6 @@ examples:
<&cpu3intc 7>,
<&cpu4intc 7>;
reg = <0xac000000 0x00010000>;
+ reg-names = "mtimecmp";
};
...
--
2.43.0
Patches currently in stable-queue which might be from inochiama@xxxxxxxxxxx are
queue-6.7/dt-bindings-timer-thead-c900-aclint-mtimer-separate-mtime-and-mtimecmp-regs.patch
