Patch "drivers: clk: zynqmp: calculate closest mux rate" has been added to the 5.15-stable tree

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This is a note to let you know that I've just added the patch titled

    drivers: clk: zynqmp: calculate closest mux rate

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drivers-clk-zynqmp-calculate-closest-mux-rate.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit f70333fa958e1aee566c5f1627502380b4a40db1
Author: Jay Buddhabhatti <jay.buddhabhatti@xxxxxxx>
Date:   Wed Nov 29 03:29:15 2023 -0800

    drivers: clk: zynqmp: calculate closest mux rate
    
    [ Upstream commit b782921ddd7f84f524723090377903f399fdbbcb ]
    
    Currently zynqmp clock driver is not calculating closest mux rate and
    because of that Linux is not setting proper frequency for CPU and
    not able to set given frequency for dynamic frequency scaling.
    
    E.g., In current logic initial acpu clock parent and frequency as below
    apll1                  0    0    0  2199999978    0     0  50000      Y
        acpu0_mux          0    0    0  2199999978    0     0  50000      Y
            acpu0_idiv1    0    0    0  2199999978    0     0  50000      Y
                acpu0      0    0    0  2199999978    0     0  50000      Y
    
    After changing acpu frequency to 549999994 Hz using CPU freq scaling its
    selecting incorrect parent which is not closest frequency.
    rpll_to_xpd            0    0    0  1599999984    0     0  50000      Y
        acpu0_mux          0    0    0  1599999984    0     0  50000      Y
            acpu0_div1     0    0    0   533333328    0     0  50000      Y
                acpu0      0    0    0   533333328    0     0  50000      Y
    
    Parent should remain same since 549999994 = 2199999978 / 4.
    
    So use __clk_mux_determine_rate_closest() generic function to calculate
    closest rate for mux clock. After this change its selecting correct
    parent and correct clock rate.
    apll1                  0    0    0  2199999978    0     0  50000      Y
        acpu0_mux          0    0    0  2199999978    0     0  50000      Y
            acpu0_div1     0    0    0   549999995    0     0  50000      Y
                acpu0      0    0    0   549999995    0     0  50000      Y
    
    Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
    Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xxxxxxx>
    Link: https://lore.kernel.org/r/20231129112916.23125-2-jay.buddhabhatti@xxxxxxx
    Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
index 17afce594f28..5a040f939056 100644
--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
@@ -89,7 +89,7 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
 static const struct clk_ops zynqmp_clk_mux_ops = {
 	.get_parent = zynqmp_clk_mux_get_parent,
 	.set_parent = zynqmp_clk_mux_set_parent,
-	.determine_rate = __clk_mux_determine_rate,
+	.determine_rate = __clk_mux_determine_rate_closest,
 };
 
 static const struct clk_ops zynqmp_clk_mux_ro_ops = {




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