Patch "clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-renesas-rzg2l-cpg-reuse-code-in-rzg2l_cpg_reset.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 128806e9c7840373cb3ef94f4910f4c5e44ba855
Author: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Date:   Mon Nov 20 09:00:11 2023 +0200

    clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()
    
    [ Upstream commit 5f9e29b9159a41fcf6733c3b59fa46a90ce3ae20 ]
    
    Code in rzg2l_cpg_reset() is equivalent with the combined code of
    rzg2l_cpg_assert() and rzg2l_cpg_deassert(). There is no need to have
    different versions thus re-use rzg2l_cpg_assert() and rzg2l_cpg_deassert().
    
    Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
    Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20231120070024.4079344-2-claudiu.beznea.uj@xxxxxxxxxxxxxx
    Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
    Stable-dep-of: da235d2fac21 ("clk: renesas: rzg2l: Check reset monitor registers")
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 84767cfc1e73..93720f319409 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1115,29 +1115,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
 
 #define rcdev_to_priv(x)	container_of(x, struct rzg2l_cpg_priv, rcdev)
 
-static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
-			   unsigned long id)
-{
-	struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
-	const struct rzg2l_cpg_info *info = priv->info;
-	unsigned int reg = info->resets[id].off;
-	u32 dis = BIT(info->resets[id].bit);
-	u32 we = dis << 16;
-
-	dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
-
-	/* Reset module */
-	writel(we, priv->base + CLK_RST_R(reg));
-
-	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
-	udelay(35);
-
-	/* Release module from reset state */
-	writel(we | dis, priv->base + CLK_RST_R(reg));
-
-	return 0;
-}
-
 static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
 			    unsigned long id)
 {
@@ -1168,6 +1145,21 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
 	return 0;
 }
 
+static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
+			   unsigned long id)
+{
+	int ret;
+
+	ret = rzg2l_cpg_assert(rcdev, id);
+	if (ret)
+		return ret;
+
+	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
+	udelay(35);
+
+	return rzg2l_cpg_deassert(rcdev, id);
+}
+
 static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
 			    unsigned long id)
 {




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