This is a note to let you know that I've just added the patch titled
arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digits
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-dts-qcom-ipq6018-pad-addresses-to-8-hex-digits.patch
and it can be found in the queue-6.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit f1e3e35bafdb162441baede2c551c7d5bbe40194
Author: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Date: Mon Jan 2 10:46:26 2023 +0100
arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digits
[ Upstream commit 647380e41520c7dbd651ebf0d9fd7dfa4928f42d ]
Some addresses were 7-hex-digits long, or less. Fix that.
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20230102094642.74254-2-konrad.dybcio@xxxxxxxxxx
Stable-dep-of: 5c0dbe8b0584 ("arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK")
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 55f685f51c71..43a948b64007 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -146,7 +146,7 @@ reserved-memory {
ranges;
rpm_msg_ram: memory@60000 {
- reg = <0x0 0x60000 0x0 0x6000>;
+ reg = <0x0 0x00060000 0x0 0x6000>;
no-map;
};
@@ -181,7 +181,7 @@ soc: soc {
prng: qrng@e1000 {
compatible = "qcom,prng-ee";
- reg = <0x0 0xe3000 0x0 0x1000>;
+ reg = <0x0 0x000e3000 0x0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
@@ -388,7 +388,7 @@ v2m@0 {
pcie_phy: phy@84000 {
compatible = "qcom,ipq6018-qmp-pcie-phy";
- reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
@@ -404,10 +404,10 @@ pcie_phy: phy@84000 {
"common";
pcie_phy0: phy@84200 {
- reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
- <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
- <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
- <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */
+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
@@ -629,7 +629,7 @@ mdio: mdio@90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
- reg = <0x0 0x90000 0x0 0x64>;
+ reg = <0x0 0x00090000 0x0 0x64>;
clocks = <&gcc GCC_MDIO_AHB_CLK>;
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
@@ -637,7 +637,7 @@ mdio: mdio@90000 {
qusb_phy_1: qusb@59000 {
compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x059000 0x0 0x180>;
+ reg = <0x0 0x00059000 0x0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
@@ -670,7 +670,7 @@ usb2: usb@70f8800 {
dwc_1: usb@7000000 {
compatible = "snps,dwc3";
- reg = <0x0 0x7000000 0x0 0xcd00>;
+ reg = <0x0 0x07000000 0x0 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>;
phy-names = "usb2-phy";
@@ -685,7 +685,7 @@ dwc_1: usb@7000000 {
ssphy_0: ssphy@78000 {
compatible = "qcom,ipq6018-qmp-usb3-phy";
- reg = <0x0 0x78000 0x0 0x1c4>;
+ reg = <0x0 0x00078000 0x0 0x1c4>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -714,7 +714,7 @@ usb0_ssphy: phy@78200 {
qusb_phy_0: qusb@79000 {
compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x079000 0x0 0x180>;
+ reg = <0x0 0x00079000 0x0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
