Patch "arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-qcom-ipq6018-improve-pcie-phy-pcs-reg-tabl.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 3478643b96d58a8d739210cce5bea96b60a7cd15
Author: Christian Marangi <ansuelsmth@xxxxxxxxx>
Date:   Thu Nov 3 22:21:25 2022 +0100

    arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table
    
    [ Upstream commit 08f399a818b0eff552b1f23c3171950a58aea78f ]
    
    This is not a fix on its own but more a cleanup. Phy qmp pcie driver
    currently have a workaround to handle pcs_misc not declared and add
    0x400 offset to the pcs reg if pcs_misc is not declared.
    
    Correctly declare pcs_misc reg and reduce PCS size to the common value
    of 0x1f0 as done for every other qmp based pcie phy device.
    
    Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
    Reviewed-by: Vinod Koul <vkoul@xxxxxxxxxx>
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20221103212125.17156-2-ansuelsmth@xxxxxxxxx
    Stable-dep-of: 5c0dbe8b0584 ("arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK")
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index d436fa64caad..f3743ef7354f 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -406,7 +406,8 @@ pcie_phy: phy@84000 {
 			pcie_phy0: phy@84200 {
 				reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
 				      <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
-				      <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
+				      <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
+				      <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */
 				#phy-cells = <0>;
 
 				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;




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