Patch "arm64: dts: qcom: sc8180x: Fix up PCIe nodes" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64: dts: qcom: sc8180x: Fix up PCIe nodes

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-qcom-sc8180x-fix-up-pcie-nodes.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit b27c5127c4d118d74aeaaae250106fdd53578412
Author: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Date:   Tue Dec 19 14:05:06 2023 +0100

    arm64: dts: qcom: sc8180x: Fix up PCIe nodes
    
    [ Upstream commit 78403b37f6770441f80a78d13772394731afe055 ]
    
    Duplicated clock output names cause probe errors and wrong clocks cause
    hardware not to work. Fix such issues.
    
    Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances")
    Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20231219-topic-8180_pcie-v1-1-c2acbba4723c@xxxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index dfaeb337960e..f4381424e70a 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -1762,7 +1762,7 @@ pcie0_phy: phy@1c06000 {
 			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_0_CLKREF_CLK>,
-				 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+				 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
 				 <&gcc GCC_PCIE_0_PIPE_CLK>;
 			clock-names = "aux",
 				      "cfg_ahb",
@@ -1860,7 +1860,7 @@ pcie3_phy: phy@1c0c000 {
 			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 				 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_3_CLKREF_CLK>,
-				 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+				 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
 				 <&gcc GCC_PCIE_3_PIPE_CLK>;
 			clock-names = "aux",
 				      "cfg_ahb",
@@ -2066,7 +2066,7 @@ pcie2_phy: phy@1c1c000 {
 				      "refgen",
 				      "pipe";
 			#clock-cells = <0>;
-			clock-output-names = "pcie_3_pipe_clk";
+			clock-output-names = "pcie_2_pipe_clk";
 
 			#phy-cells = <0>;
 




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