This is a note to let you know that I've just added the patch titled
clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs
to the 6.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-qcom-gcc-sm8550-use-collapse-voting-for-pcie-gds.patch
and it can be found in the queue-6.7 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit 1de85c5c344e33e7e34f205e8960e59a841d27b7
Author: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Date: Mon Dec 18 17:02:06 2023 +0100
clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs
[ Upstream commit 7e77a39265293ea4f05e20fff180755503c49918 ]
The PCIe GDSCs can be shared with other masters and should use the APCS
collapse-vote register when updating the power state.
This is specifically also needed to be able to disable power domains
that have been enabled by boot firmware using the vote register.
Following other recent Qualcomm platforms, describe this register and
the corresponding mask for the PCIe (and _phy) GDSCs.
Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550")
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-5-ce1272d77540@xxxxxxxxxx
Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index a16d07426b71..73bda0d03aa7 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -2998,6 +2998,8 @@ static struct clk_branch gcc_video_axi1_clk = {
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
+ .collapse_ctrl = 0x52020,
+ .collapse_mask = BIT(0),
.pd = {
.name = "pcie_0_gdsc",
},
@@ -3007,6 +3009,8 @@ static struct gdsc pcie_0_gdsc = {
static struct gdsc pcie_0_phy_gdsc = {
.gdscr = 0x6c000,
+ .collapse_ctrl = 0x52020,
+ .collapse_mask = BIT(3),
.pd = {
.name = "pcie_0_phy_gdsc",
},
@@ -3016,6 +3020,8 @@ static struct gdsc pcie_0_phy_gdsc = {
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x8d004,
+ .collapse_ctrl = 0x52020,
+ .collapse_mask = BIT(1),
.pd = {
.name = "pcie_1_gdsc",
},
@@ -3025,6 +3031,8 @@ static struct gdsc pcie_1_gdsc = {
static struct gdsc pcie_1_phy_gdsc = {
.gdscr = 0x8e000,
+ .collapse_ctrl = 0x52020,
+ .collapse_mask = BIT(4),
.pd = {
.name = "pcie_1_phy_gdsc",
},
