Patch "ASoC: fsl_xcvr: refine the requested phy clock frequency" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    ASoC: fsl_xcvr: refine the requested phy clock frequency

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     asoc-fsl_xcvr-refine-the-requested-phy-clock-frequen.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 30e0c8549b61b79a4b72431f11d564e67f436cd3
Author: Shengjiu Wang <shengjiu.wang@xxxxxxx>
Date:   Thu Nov 23 09:14:53 2023 +0800

    ASoC: fsl_xcvr: refine the requested phy clock frequency
    
    [ Upstream commit 347ecf29a68cc8958fbcbd26ef410d07fe9d82f4 ]
    
    As the input phy clock frequency will divided by 2 by default
    on i.MX8MP with the implementation of clk-imx8mp-audiomix driver,
    So the requested frequency need to be updated.
    
    The relation of phy clock is:
        sai_pll_ref_sel
           sai_pll
              sai_pll_bypass
                 sai_pll_out
                    sai_pll_out_div2
                       earc_phy_cg
    
    Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx>
    Reviewed-by: Iuliana Prodan <iuliana.prodan@xxxxxxx>
    Link: https://lore.kernel.org/r/1700702093-8008-1-git-send-email-shengjiu.wang@xxxxxxx
    Signed-off-by: Mark Brown <broonie@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index 77f8e2394bf9..f0fb33d719c2 100644
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -358,7 +358,7 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
 	struct device *dev = &xcvr->pdev->dev;
 	int ret;
 
-	freq = xcvr->soc_data->spdif_only ? freq / 10 : freq;
+	freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
 	clk_disable_unprepare(xcvr->phy_clk);
 	ret = clk_set_rate(xcvr->phy_clk, freq);
 	if (ret < 0) {
@@ -409,7 +409,7 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 	u32 m_ctl = 0, v_ctl = 0;
 	u32 r = substream->runtime->rate, ch = substream->runtime->channels;
-	u32 fout = 32 * r * ch * 10 * 2;
+	u32 fout = 32 * r * ch * 10;
 	int ret = 0;
 
 	switch (xcvr->mode) {




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