Patch "clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-rockchip-rk3128-fix-sclk_sdmmc-s-clock-name.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 054db749f3a26ece5c1e3b35644ff2e55f99a28f
Author: Alex Bee <knaerzche@xxxxxxxxx>
Date:   Mon Nov 27 19:14:18 2023 +0100

    clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name
    
    [ Upstream commit 99fe9ee56bd2f7358f1bc72551c2f3a6bbddf80a ]
    
    SCLK_SDMMC is the parent for SCLK_SDMMC_DRV and SCLK_SDMMC_SAMPLE, but
    used with the (more) correct name sclk_sdmmc. SD card tuning does currently
    fail as the parent can't be found under that name.
    There is no need to suffix the name with '0' since RK312x SoCs do have a
    single sdmmc controller - so rename it to the name which is already used
    by it's children.
    
    Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
    Signed-off-by: Alex Bee <knaerzche@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20231127181415.11735-6-knaerzche@xxxxxxxxx
    Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index fcacfe758829c..22e7522360307 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -310,7 +310,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
 	GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,
 			RK2928_CLKGATE_CON(2), 15, GFLAGS),
 
-	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
+	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
 			RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
 			RK2928_CLKGATE_CON(2), 11, GFLAGS),
 




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