Patch "drm/i915/mtl: Fix HDMI/DP PLL clock selection" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/i915/mtl: Fix HDMI/DP PLL clock selection

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-i915-mtl-fix-hdmi-dp-pll-clock-selection.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit f0997cda38dc316a50abbca1977ed05bb624148b
Author: Imre Deak <imre.deak@xxxxxxxxx>
Date:   Thu Dec 14 00:05:26 2023 +0200

    drm/i915/mtl: Fix HDMI/DP PLL clock selection
    
    [ Upstream commit dbcab554f777390d9bb6a808ed0cd90ee59bb44e ]
    
    Select the HDMI specific PLL clock only for HDMI outputs.
    
    Fixes: 62618c7f117e ("drm/i915/mtl: C20 PLL programming")
    Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
    Cc: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
    Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
    Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
    Link: https://patchwork.freedesktop.org/patch/msgid/20231213220526.1828827-1-imre.deak@xxxxxxxxx
    (cherry picked from commit 937d02cc79c6828fef28a4d80d8d0ad2f7bf2b62)
    Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 80e4ec6ee4031..048e581fda16c 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2420,7 +2420,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 
 	val |= XELPDP_FORWARD_CLOCK_UNGATE;
 
-	if (is_hdmi_frl(crtc_state->port_clock))
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+	    is_hdmi_frl(crtc_state->port_clock))
 		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
 	else
 		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);




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