Patch "octeontx2-af: Update Tx link register range" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    octeontx2-af: Update Tx link register range

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     octeontx2-af-update-tx-link-register-range.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 5be70ab09ba5ca55e550cafd875dfd84d1e06ddf
Author: Rahul Bhansali <rbhansali@xxxxxxxxxxx>
Date:   Tue Dec 5 13:34:34 2023 +0530

    octeontx2-af: Update Tx link register range
    
    [ Upstream commit 7336fc196748f82646b630d5a2e9d283e200b988 ]
    
    On new silicons the TX channels for transmit level has increased.
    This patch fixes the respective register offset range to
    configure the newly added channels.
    
    Fixes: b279bbb3314e ("octeontx2-af: NIX Tx scheduler queue config support")
    Signed-off-by: Rahul Bhansali <rbhansali@xxxxxxxxxxx>
    Signed-off-by: Geetha sowjanya <gakula@xxxxxxxxxxx>
    Reviewed-by: Wojciech Drewek <wojciech.drewek@xxxxxxxxx>
    Signed-off-by: Paolo Abeni <pabeni@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
index b3150f0532919..d46ac29adb966 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
@@ -31,8 +31,8 @@ static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = {
 	{NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
 			      {0x1200, 0x12E0} } },
 	{NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
-			      {0x1610, 0x1618}, {0x1700, 0x17B0} } },
-	{NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17B0} } },
+			      {0x1610, 0x1618}, {0x1700, 0x17C8} } },
+	{NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
 	{NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
 };
 




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