Patch "clocksource/drivers/timer-atmel-tcb: Fix initialization on SAM9 hardware" has been added to the 5.15-stable tree

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This is a note to let you know that I've just added the patch titled

    clocksource/drivers/timer-atmel-tcb: Fix initialization on SAM9 hardware

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clocksource-drivers-timer-atmel-tcb-fix-initializati.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit f4658a97e95519289aba2120e89908dbd0043d82
Author: Ronald Wahl <ronald.wahl@xxxxxxxxxxx>
Date:   Sat Oct 7 18:17:13 2023 +0200

    clocksource/drivers/timer-atmel-tcb: Fix initialization on SAM9 hardware
    
    [ Upstream commit 6d3bc4c02d59996d1d3180d8ed409a9d7d5900e0 ]
    
    On SAM9 hardware two cascaded 16 bit timers are used to form a 32 bit
    high resolution timer that is used as scheduler clock when the kernel
    has been configured that way (CONFIG_ATMEL_CLOCKSOURCE_TCB).
    
    The driver initially triggers a reset-to-zero of the two timers but this
    reset is only performed on the next rising clock. For the first timer
    this is ok - it will be in the next 60ns (16MHz clock). For the chained
    second timer this will only happen after the first timer overflows, i.e.
    after 2^16 clocks (~4ms with a 16MHz clock). So with other words the
    scheduler clock resets to 0 after the first 2^16 clock cycles.
    
    It looks like that the scheduler does not like this and behaves wrongly
    over its lifetime, e.g. some tasks are scheduled with a long delay. Why
    that is and if there are additional requirements for this behaviour has
    not been further analysed.
    
    There is a simple fix for resetting the second timer as well when the
    first timer is reset and this is to set the ATMEL_TC_ASWTRG_SET bit in
    the Channel Mode register (CMR) of the first timer. This will also rise
    the TIOA line (clock input of the second timer) when a software trigger
    respective SYNC is issued.
    
    Signed-off-by: Ronald Wahl <ronald.wahl@xxxxxxxxxxx>
    Acked-by: Alexandre Belloni <alexandre.belloni@xxxxxxxxxxx>
    Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20231007161803.31342-1-rwahl@xxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 27af17c995900..2a90c92a9182a 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -315,6 +315,7 @@ static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 	writel(mck_divisor_idx			/* likely divide-by-8 */
 			| ATMEL_TC_WAVE
 			| ATMEL_TC_WAVESEL_UP		/* free-run */
+			| ATMEL_TC_ASWTRG_SET		/* TIOA0 rises at software trigger */
 			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
 			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
 			tcaddr + ATMEL_TC_REG(0, CMR));



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