This is a note to let you know that I've just added the patch titled
clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-renesas-rzg2l-wait-for-status-bit-of-sd-mux-befo.patch
and it can be found in the queue-6.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit 535e0f8b6c92332d5326e1b6db81d54c5521bb13
Author: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Date: Fri Sep 29 08:38:49 2023 +0300
clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
[ Upstream commit 549f4ae2601f968e2474c6031fb4799468882f64 ]
The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf,
chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching
Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL
for SD clock switching status.
Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Link: https://lore.kernel.org/r/20230929053915.1530607-3-claudiu.beznea@xxxxxxxxxxxxxx
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 2c877576c5729..85e49f4eb6a50 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -192,7 +192,8 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
u32 off = GET_REG_OFFSET(hwdata->conf);
u32 shift = GET_SHIFT(hwdata->conf);
const u32 clk_src_266 = 2;
- u32 bitmask;
+ u32 msk, val, bitmask;
+ int ret;
/*
* As per the HW manual, we should not directly switch from 533 MHz to
@@ -206,14 +207,10 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
* the index to value mapping is done by adding 1 to the index.
*/
bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
+ msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
if (index != clk_src_266) {
- u32 msk, val;
- int ret;
-
writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
- msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
-
ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
!(val & msk), 100,
CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
@@ -225,7 +222,13 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
writel(bitmask | ((index + 1) << shift), priv->base + off);
- return 0;
+ ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
+ !(val & msk), 100,
+ CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
+ if (ret)
+ dev_err(priv->dev, "failed to switch clk source\n");
+
+ return ret;
}
static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
