Patch "clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-ipq9574-drop-the-clk_set_rate_parent-flag-f.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit c5e99402b928a31039036dfb742ac69c816f7ee0
Author: Kathiravan Thirumoorthy <quic_kathirav@xxxxxxxxxxx>
Date:   Thu Sep 14 12:29:54 2023 +0530

    clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
    
    [ Upstream commit 99a8f8764b70158a712992640a6be46a8fd79d15 ]
    
    GPLL clock rates are fixed and shouldn't be scaled based on the request
    from dependent clocks. Doing so will result in the unexpected behaviour.
    So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.
    
    ----
    Changes in V2:
            - No changes
    
    Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
    Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@xxxxxxxxxxx>
    Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-4-c8ceb1a37680@xxxxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 8f430367299e6..e8190108e1aef 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -87,7 +87,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
 			&gpll0_main.clkr.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -102,7 +101,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
 			&gpll0_main.clkr.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
 	},
 };
@@ -132,7 +130,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
 			&gpll4_main.clkr.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
 	},
 };
@@ -162,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
 			&gpll2_main.clkr.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
 	},
 };



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