Patch "clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks" has been added to the 6.6-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-ipq5018-drop-the-clk_set_rate_parent-flag-f.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit cec338ed3fc6386393ed6ff4254e8454e0f5a041
Author: Kathiravan Thirumoorthy <quic_kathirav@xxxxxxxxxxx>
Date:   Thu Sep 14 12:29:53 2023 +0530

    clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
    
    [ Upstream commit 01a5e4c6731ab6b4b74822661d296f8893fc1230 ]
    
    GPLL clock rates are fixed and shouldn't be scaled based on the
    request from dependent clocks. Doing so will result in the unexpected
    behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.
    
    ----
    Changes in V2:
            - New patch
    
    Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")
    Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@xxxxxxxxxxx>
    Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-3-c8ceb1a37680@xxxxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
index 19dc2b71cacf0..2a3c0659b7008 100644
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -128,7 +128,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
 		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -143,7 +142,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
 		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -158,7 +156,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
 		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };