Patch "clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks" has been added to the 6.6-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-ipq5332-drop-set-rate-parent-from-gpll0-dep.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 3148d30cd065010f81f71f51aab086bdbfa675b8
Author: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
Date:   Thu Aug 31 14:58:53 2023 +0530

    clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks
    
    [ Upstream commit ccd8ab030643040600a663edde56b434b6f4fb6c ]
    
    IPQ5332's GPLL0's nominal/turbo frequency is 800MHz.
    This must not be scaled based on the requirement of
    dependent clocks. Hence remove the CLK_SET_RATE_PARENT
    flag.
    
    Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC")
    Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
    Reviewed-by: Kathiravan T <quic_kathirav@xxxxxxxxxxx>
    Link: https://lore.kernel.org/r/1693474133-10467-1-git-send-email-quic_varada@xxxxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index b02026f8549b2..b836159fbdefa 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -71,7 +71,6 @@ static struct clk_fixed_factor gpll0_div2 = {
 				&gpll0_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_fixed_factor_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -85,7 +84,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
 				&gpll0_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };