Patch "clk: renesas: rzg2l: Trust value returned by hardware" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: renesas: rzg2l: Trust value returned by hardware

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-renesas-rzg2l-trust-value-returned-by-hardware.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit c4b054255f5c21fa069dfb689f44a87240529241
Author: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Date:   Fri Sep 29 08:38:51 2023 +0300

    clk: renesas: rzg2l: Trust value returned by hardware
    
    [ Upstream commit bf51d3b2d048c312764a55d91d67a85ee5535e31 ]
    
    The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b.  The
    hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that
    setting 0 is prohibited.  Hence rzg2l_cpg_sd_clk_mux_get_parent() should
    just read CPG_PL2SDHI_DSEL, trust the value, and return the proper clock
    parent index based on the value read.
    
    Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
    Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
    Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20230929053915.1530607-5-claudiu.beznea@xxxxxxxxxxxxxx
    Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 4c1f388ded6b2..2058a7e3a6aad 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -238,14 +238,8 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
 
 	val >>= GET_SHIFT(hwdata->conf);
 	val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0);
-	if (val) {
-		val--;
-	} else {
-		/* Prohibited clk source, change it to 533 MHz(reset value) */
-		rzg2l_cpg_sd_clk_mux_set_parent(hw, 0);
-	}
 
-	return val;
+	return val ? val - 1 : 0;
 }
 
 static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = {



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