This is a note to let you know that I've just added the patch titled
riscv: dts: thead: set dma-noncoherent to soc bus
to the 6.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
riscv-dts-thead-set-dma-noncoherent-to-soc-bus.patch
and it can be found in the queue-6.5 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit ac0b02cd3004f6f56416ccb3a6589d7bb86fe612
Author: Jisheng Zhang <jszhang@xxxxxxxxxx>
Date: Tue Sep 12 15:22:32 2023 +0800
riscv: dts: thead: set dma-noncoherent to soc bus
[ Upstream commit 759426c758c7053a941a4c06c7571461439fcff6 ]
riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.
Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
Tested-by: Drew Fustini <dfustini@xxxxxxxxxxxx>
Reviewed-by: Guo Ren <guoren@xxxxxxxxxx>
Signed-off-by: Arnd Bergmann <arnd@xxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 56a73134b49e6..58108f0eb3fdc 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -139,6 +139,7 @@ soc {
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
+ dma-noncoherent;
ranges;
plic: interrupt-controller@ffd8000000 {
