Patch "riscv: errata: fix T-Head dcache.cva encoding" has been added to the 6.5-stable tree

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This is a note to let you know that I've just added the patch titled

    riscv: errata: fix T-Head dcache.cva encoding

to the 6.5-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     riscv-errata-fix-t-head-dcache.cva-encoding.patch
and it can be found in the queue-6.5 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 6340f103eacbc4416be85eab0589c92345c7997b
Author: Icenowy Zheng <uwu@xxxxxxxxxx>
Date:   Tue Sep 12 15:24:10 2023 +0800

    riscv: errata: fix T-Head dcache.cva encoding
    
    [ Upstream commit 8eb8fe67e2c84324398f5983c41b4f831d0705b3 ]
    
    The dcache.cva encoding shown in the comments are wrong, it's for
    dcache.cval1 (which is restricted to L1) instead.
    
    Fix this in the comment and in the hardcoded instruction.
    
    Signed-off-by: Icenowy Zheng <uwu@xxxxxxxxxx>
    Tested-by: Sergey Matyukevich <sergey.matyukevich@xxxxxxxxxxxxx>
    Reviewed-by: Heiko Stuebner <heiko@xxxxxxxxx>
    Reviewed-by: Guo Ren <guoren@xxxxxxxxxx>
    Tested-by: Drew Fustini <dfustini@xxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20230912072410.2481-1-jszhang@xxxxxxxxxx
    Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index fb1a810f3d8ce..feab334dd8329 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE(						\
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01001      rs1       000      00000  0001011
  * dcache.cva rs1 (clean, virtual address)
- *   0000001    00100      rs1       000      00000  0001011
+ *   0000001    00101      rs1       000      00000  0001011
  *
  * dcache.cipa rs1 (clean then invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
@@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE(						\
  *   0000000    11001     00000      000      00000  0001011
  */
 #define THEAD_inval_A0	".long 0x0265000b"
-#define THEAD_clean_A0	".long 0x0245000b"
+#define THEAD_clean_A0	".long 0x0255000b"
 #define THEAD_flush_A0	".long 0x0275000b"
 #define THEAD_SYNC_S	".long 0x0190000b"
 



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