Patch "perf/imx_ddr: speed up overflow frequency of cycle" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    perf/imx_ddr: speed up overflow frequency of cycle

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     perf-imx_ddr-speed-up-overflow-frequency-of-cycle.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 9b95d1939fa4cfdad52df3b5f37d31da1db6d67b
Author: Xu Yang <xu.yang_2@xxxxxxx>
Date:   Fri Aug 11 09:54:37 2023 +0800

    perf/imx_ddr: speed up overflow frequency of cycle
    
    [ Upstream commit e89ecd8368860bf05437eabd07d292c316221cfc ]
    
    For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least
    4 times as often as other events. Due to byte counters will count for any
    event configured, it will overflow more often. And if byte counters
    overflow that related counters would stop since they share the
    COUNTER_CNTL. We can speed up cycle counter overflow frequency by setting
    counter parameter (CP) field of cycle counter. In this way, we can avoid
    stop counting byte counters when interrupt didn't come and the byte
    counters can be fetched or updated from each cycle counter overflow
    interrupt.
    
    Because we initialize CP filed to shorten counter0 overflow time, the cycle
    counter will start couting from a fixed/base value each time. We need to
    remove the base from the result too. Therefore, we could get precise result
    from cycle counter.
    
    Signed-off-by: Xu Yang <xu.yang_2@xxxxxxx>
    Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
    Link: https://lore.kernel.org/r/20230811015438.1999307-1-xu.yang_2@xxxxxxx
    Signed-off-by: Will Deacon <will@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
index cd4ce2b4906d1..a4cda73b81c9f 100644
--- a/drivers/perf/fsl_imx8_ddr_perf.c
+++ b/drivers/perf/fsl_imx8_ddr_perf.c
@@ -28,6 +28,8 @@
 #define CNTL_CLEAR_MASK		0xFFFFFFFD
 #define CNTL_OVER_MASK		0xFFFFFFFE
 
+#define CNTL_CP_SHIFT		16
+#define CNTL_CP_MASK		(0xFF << CNTL_CP_SHIFT)
 #define CNTL_CSV_SHIFT		24
 #define CNTL_CSV_MASK		(0xFFU << CNTL_CSV_SHIFT)
 
@@ -35,6 +37,8 @@
 #define EVENT_CYCLES_COUNTER	0
 #define NUM_COUNTERS		4
 
+/* For removing bias if cycle counter CNTL.CP is set to 0xf0 */
+#define CYCLES_COUNTER_MASK	0x0FFFFFFF
 #define AXI_MASKING_REVERT	0xffff0000	/* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */
 
 #define to_ddr_pmu(p)		container_of(p, struct ddr_pmu, pmu)
@@ -429,6 +433,17 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
 		writel(0, pmu->base + reg);
 		val = CNTL_EN | CNTL_CLEAR;
 		val |= FIELD_PREP(CNTL_CSV_MASK, config);
+
+		/*
+		 * On i.MX8MP we need to bias the cycle counter to overflow more often.
+		 * We do this by initializing bits [23:16] of the counter value via the
+		 * COUNTER_CTRL Counter Parameter (CP) field.
+		 */
+		if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
+			if (counter == EVENT_CYCLES_COUNTER)
+				val |= FIELD_PREP(CNTL_CP_MASK, 0xf0);
+		}
+
 		writel(val, pmu->base + reg);
 	} else {
 		/* Disable counter */
@@ -468,6 +483,12 @@ static void ddr_perf_event_update(struct perf_event *event)
 	int ret;
 
 	new_raw_count = ddr_perf_read_counter(pmu, counter);
+	/* Remove the bias applied in ddr_perf_counter_enable(). */
+	if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
+		if (counter == EVENT_CYCLES_COUNTER)
+			new_raw_count &= CYCLES_COUNTER_MASK;
+	}
+
 	local64_add(new_raw_count, &event->count);
 
 	/*



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