Patch "usb: dwc3: dwc3-octeon: Verify clock divider" has been added to the 6.5-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    usb: dwc3: dwc3-octeon: Verify clock divider

to the 6.5-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     usb-dwc3-dwc3-octeon-verify-clock-divider.patch
and it can be found in the queue-6.5 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit c151f6712e0b82f9f120a8da356633024f4459e0
Author: Ladislav Michl <ladis@xxxxxxxxxxxxxx>
Date:   Tue Aug 8 11:37:50 2023 +0200

    usb: dwc3: dwc3-octeon: Verify clock divider
    
    [ Upstream commit fb57f829beefd4b3746f1b23d51e80ed5d4bb87b ]
    
    Although valid USB clock divider will be calculated for all valid
    Octeon core frequencies, make code formally correct limiting
    divider not to be greater that 7 so it fits into H_CLKDIV_SEL
    field.
    
    Signed-off-by: Ladislav Michl <ladis@xxxxxxxxxxxxxx>
    Reported-by: Linux Kernel Functional Testing <lkft@xxxxxxxxxx>
    Closes: https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20230808/testrun/18882876/suite/build/test/gcc-8-cavium_octeon_defconfig/log
    Acked-by: Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/ZNIM7tlBNdHFzXZG@lenoch
    Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c
index 2add435ad0387..165e032d08647 100644
--- a/arch/mips/cavium-octeon/octeon-usb.c
+++ b/arch/mips/cavium-octeon/octeon-usb.c
@@ -243,11 +243,11 @@ static int dwc3_octeon_get_divider(void)
 	while (div < ARRAY_SIZE(clk_div)) {
 		uint64_t rate = octeon_get_io_clock_rate() / clk_div[div];
 		if (rate <= 300000000 && rate >= 150000000)
-			break;
+			return div;
 		div++;
 	}
 
-	return div;
+	return -EINVAL;
 }
 
 static int dwc3_octeon_config_power(struct device *dev, void __iomem *base)
@@ -374,6 +374,10 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base)
 
 	/* Step 4b: Select controller clock frequency. */
 	div = dwc3_octeon_get_divider();
+	if (div < 0) {
+		dev_err(dev, "clock divider invalid\n");
+		return div;
+	}
 	val = dwc3_octeon_readq(uctl_ctl_reg);
 	val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;
 	val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);