Patch "PCI: Add #defines for Enter Compliance, Transmit Margin" has been added to the 5.4-stable tree

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This is a note to let you know that I've just added the patch titled

    PCI: Add #defines for Enter Compliance, Transmit Margin

to the 5.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     pci-add-defines-for-enter-compliance-transmit-margin.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit d4fc74689083af3014e33fe886507bc9bafd2d6a
Author: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Date:   Tue Nov 12 11:07:36 2019 -0600

    PCI: Add #defines for Enter Compliance, Transmit Margin
    
    [ Upstream commit bbdb2f5ecdf1e66b2f09710134db3c2e5c43a958 ]
    
    Add definitions for the Enter Compliance and Transmit Margin fields of the
    PCIe Link Control 2 register.
    
    Link: https://lore.kernel.org/r/20191112173503.176611-2-helgaas@xxxxxxxxxx
    Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
    Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL")
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index b485d8b0d5a79..5d830a95daf20 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -679,6 +679,8 @@
 #define  PCI_EXP_LNKCTL2_TLS_8_0GT	0x0003 /* Supported Speed 8GT/s */
 #define  PCI_EXP_LNKCTL2_TLS_16_0GT	0x0004 /* Supported Speed 16GT/s */
 #define  PCI_EXP_LNKCTL2_TLS_32_0GT	0x0005 /* Supported Speed 32GT/s */
+#define  PCI_EXP_LNKCTL2_ENTER_COMP	0x0010 /* Enter Compliance */
+#define  PCI_EXP_LNKCTL2_TX_MARGIN	0x0380 /* Transmit Margin */
 #define PCI_EXP_LNKSTA2		50	/* Link Status 2 */
 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	52	/* v2 endpoints with link end here */
 #define PCI_EXP_SLTCAP2		52	/* Slot Capabilities 2 */



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