Patch "PCI: microchip: Correct the DED and SEC interrupt bit offsets" has been added to the 6.5-stable tree

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This is a note to let you know that I've just added the patch titled

    PCI: microchip: Correct the DED and SEC interrupt bit offsets

to the 6.5-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     pci-microchip-correct-the-ded-and-sec-interrupt-bit-.patch
and it can be found in the queue-6.5 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit dbb57566c9dee9099bce5054f077701e9ae81fe7
Author: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
Date:   Fri Jul 28 14:13:55 2023 +0100

    PCI: microchip: Correct the DED and SEC interrupt bit offsets
    
    [ Upstream commit 6d473a5a26136edf55c435a1c433e52910e03926 ]
    
    The SEC and DED interrupt bits are laid out the wrong way round so the SEC
    interrupt handler attempts to mask, unmask, and clear the DED interrupt
    and vice versa. Correct the bit offsets so that each interrupt handler
    operates properly.
    
    Link: https://lore.kernel.org/r/20230728131401.1615724-2-daire.mcnamara@xxxxxxxxxxxxx
    Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip PolarFire PCIe controller driver")
    Signed-off-by: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
    Signed-off-by: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>
    Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
index 5e710e4854646..dd5245904c874 100644
--- a/drivers/pci/controller/pcie-microchip-host.c
+++ b/drivers/pci/controller/pcie-microchip-host.c
@@ -167,12 +167,12 @@
 #define EVENT_PCIE_DLUP_EXIT			2
 #define EVENT_SEC_TX_RAM_SEC_ERR		3
 #define EVENT_SEC_RX_RAM_SEC_ERR		4
-#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR		5
-#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR		6
+#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR		5
+#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR		6
 #define EVENT_DED_TX_RAM_DED_ERR		7
 #define EVENT_DED_RX_RAM_DED_ERR		8
-#define EVENT_DED_AXI2PCIE_RAM_DED_ERR		9
-#define EVENT_DED_PCIE2AXI_RAM_DED_ERR		10
+#define EVENT_DED_PCIE2AXI_RAM_DED_ERR		9
+#define EVENT_DED_AXI2PCIE_RAM_DED_ERR		10
 #define EVENT_LOCAL_DMA_END_ENGINE_0		11
 #define EVENT_LOCAL_DMA_END_ENGINE_1		12
 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0		13



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