Patch "drm/amd/display: Exit idle optimizations before attempt to access PHY" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amd/display: Exit idle optimizations before attempt to access PHY

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-exit-idle-optimizations-before-attem.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit a8025487bc6183ae643c7ffd47a8a40e43ddf5b9
Author: Leo Chen <sancchen@xxxxxxx>
Date:   Wed Jul 12 16:50:15 2023 -0400

    drm/amd/display: Exit idle optimizations before attempt to access PHY
    
    [ Upstream commit de612738e9771bd66aeb20044486c457c512f684 ]
    
    [Why & How]
    DMUB may hang when powering down pixel clocks due to no dprefclk.
    
    It is fixed by exiting idle optimization before the attempt to access PHY.
    
    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@xxxxxxx>
    Acked-by: Alex Hung <alex.hung@xxxxxxx>
    Signed-off-by: Leo Chen <sancchen@xxxxxxx>
    Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index d260eaa1509ed..9378c98d02cfe 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1813,10 +1813,13 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
 			hws->funcs.edp_backlight_control(edp_link_with_sink, false);
 		}
 		/*resume from S3, no vbios posting, no need to power down again*/
+		clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
+
 		power_down_all_hw_blocks(dc);
 		disable_vga_and_power_gate_all_controllers(dc);
 		if (edp_link_with_sink && !keep_edp_vdd_on)
 			dc->hwss.edp_power_control(edp_link_with_sink, false);
+		clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 	}
 	bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
 }



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