Patch "drm/i915/gt: Poll aux invalidation register bit on invalidation" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/i915/gt: Poll aux invalidation register bit on invalidation

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-i915-gt-poll-aux-invalidation-register-bit-on-in.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 9201c3eac1e955be13872cdeed28cbfb9bd33474
Author: Jonathan Cavitt <jonathan.cavitt@xxxxxxxxx>
Date:   Tue Jul 25 02:19:49 2023 +0200

    drm/i915/gt: Poll aux invalidation register bit on invalidation
    
    [ Upstream commit 0fde2f23516a00fd90dfb980b66b4665fcbfa659 ]
    
    For platforms that use Aux CCS, wait for aux invalidation to
    complete by checking the aux invalidation register bit is
    cleared.
    
    Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
    Signed-off-by: Jonathan Cavitt <jonathan.cavitt@xxxxxxxxx>
    Signed-off-by: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx>
    Cc: <stable@xxxxxxxxxxxxxxx> # v5.8+
    Reviewed-by: Nirmoy Das <nirmoy.das@xxxxxxxxx>
    Reviewed-by: Andrzej Hajda <andrzej.hajda@xxxxxxxxx>
    Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
    Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-7-andi.shyti@xxxxxxxxxxxxxxx
    (cherry picked from commit d459c86f00aa98028d155a012c65dc42f7c37e76)
    Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 6a8c2fab4ca81..975e31d876b1a 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -184,7 +184,15 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
 	*cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
 	*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
 	*cs++ = AUX_INV;
-	*cs++ = MI_NOOP;
+
+	*cs++ = MI_SEMAPHORE_WAIT_TOKEN |
+		MI_SEMAPHORE_REGISTER_POLL |
+		MI_SEMAPHORE_POLL |
+		MI_SEMAPHORE_SAD_EQ_SDD;
+	*cs++ = 0;
+	*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
+	*cs++ = 0;
+	*cs++ = 0;
 
 	return cs;
 }
@@ -252,10 +260,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 		else if (engine->class == COMPUTE_CLASS)
 			flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
 
+		count = 8;
 		if (gen12_needs_ccs_aux_inv(rq->engine))
-			count = 8 + 4;
-		else
-			count = 8;
+			count += 8;
 
 		cs = intel_ring_begin(rq, count);
 		if (IS_ERR(cs))
@@ -298,7 +305,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
 			aux_inv = rq->engine->mask &
 				~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
 			if (aux_inv)
-				cmd += 4;
+				cmd += 8;
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index d4e9702d3c8e7..25ea5f8a464a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -120,6 +120,7 @@
 #define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
 #define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
 #define MI_SEMAPHORE_WAIT_TOKEN	MI_INSTR(0x1c, 3) /* GEN12+ */
+#define   MI_SEMAPHORE_REGISTER_POLL	(1 << 16)
 #define   MI_SEMAPHORE_POLL		(1 << 15)
 #define   MI_SEMAPHORE_SAD_GT_SDD	(0 << 12)
 #define   MI_SEMAPHORE_SAD_GTE_SDD	(1 << 12)



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