This is a note to let you know that I've just added the patch titled
drm/amd/pm/smu7: move variables to where they are used
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-amd-pm-smu7-move-variables-to-where-they-are-used.patch
and it can be found in the queue-6.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 63a9ab264a8c030482ab9e7e20b6c4c162299531 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Mon, 6 Feb 2023 11:47:47 -0500
Subject: drm/amd/pm/smu7: move variables to where they are used
From: Alex Deucher <alexander.deucher@xxxxxxx>
commit 63a9ab264a8c030482ab9e7e20b6c4c162299531 upstream.
Move variable declarations to where they are used. Fixes
a segfault on smu7 V0 structures where some tables don't
exist.
Cc: Evan Quan <evan.quan@xxxxxxx>
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2388
Fixes: b1a9557a7d00 ("drm/amd/pm: fulfill powerplay peak profiling mode shader/memory clock settings")
Reviewed-by: Evan Quan <evan.quan@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1505,12 +1505,6 @@ static void smu7_populate_umdpstate_cloc
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
- struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk =
- hwmgr->dyn_state.vddc_dependency_on_sclk;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk =
- table_info->vdd_dep_on_sclk;
int32_t tmp_sclk, count, percentage;
if (golden_dpm_table->mclk_table.count == 1) {
@@ -1525,6 +1519,9 @@ static void smu7_populate_umdpstate_cloc
tmp_sclk = hwmgr->pstate_mclk * percentage / 100;
if (hwmgr->pp_table_version == PP_TABLE_V0) {
+ struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk =
+ hwmgr->dyn_state.vddc_dependency_on_sclk;
+
for (count = vddc_dependency_on_sclk->count - 1; count >= 0; count--) {
if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) {
hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk;
@@ -1537,6 +1534,11 @@ static void smu7_populate_umdpstate_cloc
hwmgr->pstate_sclk_peak =
vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk;
} else if (hwmgr->pp_table_version == PP_TABLE_V1) {
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk =
+ table_info->vdd_dep_on_sclk;
+
for (count = vdd_dep_on_sclk->count - 1; count >= 0; count--) {
if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) {
hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk;
Patches currently in stable-queue which might be from alexander.deucher@xxxxxxx are
queue-6.1/drm-amd-display-update-otg-instance-in-the-commit-stream.patch
queue-6.1/drm-amd-display-add-function-for-validate-and-update-new-stream.patch
queue-6.1/drm-amd-disable-s-g-for-apus-when-64gb-or-more-host-memory.patch
queue-6.1/drm-amdgpu-add-s-g-display-parameter.patch
queue-6.1/drm-amd-pm-avoid-unintentional-shutdown-due-to-temperature-momentary-fluctuation.patch
queue-6.1/drm-amd-pm-fulfill-powerplay-peak-profiling-mode-shader-memory-clock-settings.patch
queue-6.1/drm-amd-display-retain-phantom-plane-stream-if-validation-fails.patch
queue-6.1/drm-amd-display-avoid-abm-when-odm-combine-is-enabled-for-edp.patch
queue-6.1/drm-amd-display-disable-phantom-otg-after-enable-for-plane-disable.patch
queue-6.1/drm-amd-display-check-attr-flag-before-set-cursor-degamma-on-dcn3.patch
queue-6.1/drm-amd-display-trigger-timing-sync-only-if-tg-is-running.patch
queue-6.1/drm-amd-pm-fulfill-swsmu-peak-profiling-mode-shader-memory-clock-settings.patch
queue-6.1/drm-amdgpu-fix-possible-uaf-in-amdgpu_cs_pass1.patch
queue-6.1/drm-amd-display-handle-seamless-boot-stream.patch
queue-6.1/drm-amd-pm-smu7-move-variables-to-where-they-are-used.patch
queue-6.1/drm-amd-display-handle-virtual-hardware-detect.patch
queue-6.1/drm-amd-display-fix-the-build-when-drm_amd_dc_dcn-is-not-set.patch
queue-6.1/drm-amd-pm-expose-swctf-threshold-setting-for-legacy-powerplay.patch
queue-6.1/drm-amd-display-use-update-plane-and-stream-routine-for-dcn32x.patch
queue-6.1/drm-amd-display-limit-dpia-link-rate-to-hbr3.patch
