Patch "arm64/fpsimd: Ensure SME storage is allocated after SVE VL changes" has been added to the 6.4-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64/fpsimd: Ensure SME storage is allocated after SVE VL changes

to the 6.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-fpsimd-ensure-sme-storage-is-allocated-after-sve-vl-changes.patch
and it can be found in the queue-6.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.


>From d4d5be94a87872421ea2569044092535aff0b886 Mon Sep 17 00:00:00 2001
From: Mark Brown <broonie@xxxxxxxxxx>
Date: Thu, 20 Jul 2023 19:38:58 +0100
Subject: arm64/fpsimd: Ensure SME storage is allocated after SVE VL changes

From: Mark Brown <broonie@xxxxxxxxxx>

commit d4d5be94a87872421ea2569044092535aff0b886 upstream.

When we reconfigure the SVE vector length we discard the backing storage
for the SVE vectors and then reallocate on next SVE use, leaving the SME
specific state alone. This means that we do not enable SME traps if they
were already disabled. That means that userspace code can enter streaming
mode without trapping, putting the task in a state where if we try to save
the state of the task we will fault.

Since the ABI does not specify that changing the SVE vector length disturbs
SME state, and since SVE code may not be aware of SME code in the process,
we shouldn't simply discard any ZA state. Instead immediately reallocate
the storage for SVE, and disable SME if we change the SVE vector length
while there is no SME state active.

Disabling SME traps on SVE vector length changes would make the overall
code more complex since we would have a state where we have valid SME state
stored but might get a SME trap.

Fixes: 9e4ab6c89109 ("arm64/sme: Implement vector length configuration prctl()s")
Reported-by: David Spickett <David.Spickett@xxxxxxx>
Signed-off-by: Mark Brown <broonie@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Link: https://lore.kernel.org/r/20230720-arm64-fix-sve-sme-vl-change-v2-1-8eea06b82d57@xxxxxxxxxx
Signed-off-by: Will Deacon <will@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
 arch/arm64/kernel/fpsimd.c |   33 +++++++++++++++++++++++++--------
 1 file changed, 25 insertions(+), 8 deletions(-)

--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -847,6 +847,8 @@ void sve_sync_from_fpsimd_zeropad(struct
 int vec_set_vector_length(struct task_struct *task, enum vec_type type,
 			  unsigned long vl, unsigned long flags)
 {
+	bool free_sme = false;
+
 	if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT |
 				     PR_SVE_SET_VL_ONEXEC))
 		return -EINVAL;
@@ -897,21 +899,36 @@ int vec_set_vector_length(struct task_st
 		task->thread.fp_type = FP_STATE_FPSIMD;
 	}
 
-	if (system_supports_sme() && type == ARM64_VEC_SME) {
-		task->thread.svcr &= ~(SVCR_SM_MASK |
-				       SVCR_ZA_MASK);
-		clear_thread_flag(TIF_SME);
+	if (system_supports_sme()) {
+		if (type == ARM64_VEC_SME ||
+		    !(task->thread.svcr & (SVCR_SM_MASK | SVCR_ZA_MASK))) {
+			/*
+			 * We are changing the SME VL or weren't using
+			 * SME anyway, discard the state and force a
+			 * reallocation.
+			 */
+			task->thread.svcr &= ~(SVCR_SM_MASK |
+					       SVCR_ZA_MASK);
+			clear_thread_flag(TIF_SME);
+			free_sme = true;
+		}
 	}
 
 	if (task == current)
 		put_cpu_fpsimd_context();
 
 	/*
-	 * Force reallocation of task SVE and SME state to the correct
-	 * size on next use:
+	 * Free the changed states if they are not in use, SME will be
+	 * reallocated to the correct size on next use and we just
+	 * allocate SVE now in case it is needed for use in streaming
+	 * mode.
 	 */
-	sve_free(task);
-	if (system_supports_sme() && type == ARM64_VEC_SME)
+	if (system_supports_sve()) {
+		sve_free(task);
+		sve_alloc(task, true);
+	}
+
+	if (free_sme)
 		sme_free(task);
 
 	task_set_vl(task, type, vl);


Patches currently in stable-queue which might be from broonie@xxxxxxxxxx are

queue-6.4/asoc-codecs-wcd938x-fix-missing-mbhc-init-error-handling.patch
queue-6.4/asoc-rt5640-fix-sleep-in-atomic-context.patch
queue-6.4/asoc-codecs-wcd938x-fix-resource-leaks-on-component-remove.patch
queue-6.4/asoc-cs35l45-select-regmap_irq.patch
queue-6.4/asoc-qdsp6-audioreach-fix-topology-probe-deferral.patch
queue-6.4/asoc-tegra-fix-amx-byte-map.patch
queue-6.4/asoc-codecs-wcd938x-fix-missing-clsh-ctrl-error-handling.patch
queue-6.4/asoc-codecs-wcd938x-fix-soundwire-initialisation-race.patch
queue-6.4/asoc-fsl_sai-disable-bit-clock-with-transmitter.patch
queue-6.4/asoc-fsl_sai-revert-asoc-fsl_sai-enable-mctl_mclk_en-bit-for-master-mode.patch
queue-6.4/asoc-tegra-fix-adx-byte-map.patch
queue-6.4/arm64-fpsimd-ensure-sme-storage-is-allocated-after-sve-vl-changes.patch
queue-6.4/regmap-drop-initial-version-of-maximum-transfer-length-fixes.patch
queue-6.4/asoc-codecs-wcd934x-fix-resource-leaks-on-component-remove.patch
queue-6.4/asoc-cs42l51-fix-driver-to-properly-autoload-with-automatic-module-loading.patch
queue-6.4/asoc-codecs-wcd938x-fix-codec-initialisation-race.patch
queue-6.4/asoc-codecs-wcd-mbhc-v2-fix-resource-leaks-on-component-remove.patch
queue-6.4/regmap-account-for-register-length-in-smbus-i-o-limits.patch



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