This is a note to let you know that I've just added the patch titled
drm/amd/pm: conditionally disable pcie lane/speed switching for SMU13
to the 6.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-amd-pm-conditionally-disable-pcie-lane-speed-switching-for-smu13.patch
and it can be found in the queue-6.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 31c7a3b378a136adc63296a2ff17645896fcf303 Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@xxxxxxx>
Date: Fri, 7 Jul 2023 14:31:35 -0500
Subject: drm/amd/pm: conditionally disable pcie lane/speed switching for SMU13
From: Mario Limonciello <mario.limonciello@xxxxxxx>
commit 31c7a3b378a136adc63296a2ff17645896fcf303 upstream.
Intel platforms such as Sapphire Rapids and Raptor Lake don't support
dynamic pcie lane or speed switching.
This limitation seems to carry over from one generation to another.
To be safer, disable dynamic pcie lane width and speed switching when
running on an Intel platform.
Link: https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2663
Co-developed-by: Evan Quan <evan.quan@xxxxxxx>
Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
Signed-off-by: Mario Limonciello <mario.limonciello@xxxxxxx>
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx # 6.1.x
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 42 +++++++++++++++++++++++--
1 file changed, 39 insertions(+), 3 deletions(-)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2454,6 +2454,25 @@ int smu_v13_0_mode1_reset(struct smu_con
return ret;
}
+/*
+ * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
+ * speed switching. Until we have confirmation from Intel that a specific host
+ * supports it, it's safer that we keep it disabled for all.
+ *
+ * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
+ * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
+ */
+static bool smu_v13_0_is_pcie_dynamic_switching_supported(void)
+{
+#if IS_ENABLED(CONFIG_X86)
+ struct cpuinfo_x86 *c = &cpu_data(0);
+
+ if (c->x86_vendor == X86_VENDOR_INTEL)
+ return false;
+#endif
+ return true;
+}
+
int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
uint32_t pcie_gen_cap,
uint32_t pcie_width_cap)
@@ -2461,15 +2480,32 @@ int smu_v13_0_update_pcie_parameters(str
struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
struct smu_13_0_pcie_table *pcie_table =
&dpm_context->dpm_tables.pcie_table;
+ int num_of_levels = pcie_table->num_of_link_levels;
uint32_t smu_pcie_arg;
int ret, i;
- for (i = 0; i < pcie_table->num_of_link_levels; i++) {
- if (pcie_table->pcie_gen[i] > pcie_gen_cap)
+ if (!smu_v13_0_is_pcie_dynamic_switching_supported()) {
+ if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
+ pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
+
+ if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
+ pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
+
+ /* Force all levels to use the same settings */
+ for (i = 0; i < num_of_levels; i++) {
pcie_table->pcie_gen[i] = pcie_gen_cap;
- if (pcie_table->pcie_lane[i] > pcie_width_cap)
pcie_table->pcie_lane[i] = pcie_width_cap;
+ }
+ } else {
+ for (i = 0; i < num_of_levels; i++) {
+ if (pcie_table->pcie_gen[i] > pcie_gen_cap)
+ pcie_table->pcie_gen[i] = pcie_gen_cap;
+ if (pcie_table->pcie_lane[i] > pcie_width_cap)
+ pcie_table->pcie_lane[i] = pcie_width_cap;
+ }
+ }
+ for (i = 0; i < num_of_levels; i++) {
smu_pcie_arg = i << 16;
smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
smu_pcie_arg |= pcie_table->pcie_lane[i];
Patches currently in stable-queue which might be from mario.limonciello@xxxxxxx are
queue-6.4/drm-amd-pm-conditionally-disable-pcie-lane-speed-switching-for-smu13.patch
queue-6.4/drm-amd-pm-share-the-code-around-smu13-pcie-parameters-update.patch
queue-6.4/drm-amd-display-fix-seamless-odm-transitions.patch
queue-6.4/pinctrl-amd-only-use-special-debounce-behavior-for-gpio-0.patch
queue-6.4/pinctrl-amd-unify-debounce-handling-into-amd_pinconf_set.patch
queue-6.4/drm-amd-disable-psr-su-on-parade-0803-tcon.patch
queue-6.4/drm-amd-display-edp-do-not-add-non-edid-timings.patch
queue-6.4/drm-client-send-hotplug-event-after-registering-a-client.patch
queue-6.4/pinctrl-amd-revert-pinctrl-amd-disable-and-mask-interrupts-on-probe.patch
queue-6.4/drm-amd-display-correct-dmub_fw_version-macro.patch
queue-6.4/pinctrl-amd-fix-mistake-in-handling-clearing-pins-at-startup.patch
queue-6.4/pinctrl-amd-drop-pull-up-select-configuration.patch
queue-6.4/pinctrl-amd-detect-and-mask-spurious-interrupts.patch
queue-6.4/pinctrl-amd-use-amd_pinconf_set-for-all-config-options.patch
queue-6.4/pinctrl-amd-detect-internal-gpio0-debounce-handling.patch
