This is a note to let you know that I've just added the patch titled
pinctrl: amd: Unify debounce handling into amd_pinconf_set()
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
pinctrl-amd-unify-debounce-handling-into-amd_pinconf_set.patch
and it can be found in the queue-6.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 283c5ce7da0a676f46539094d40067ad17c4f294 Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@xxxxxxx>
Date: Wed, 5 Jul 2023 08:30:05 -0500
Subject: pinctrl: amd: Unify debounce handling into amd_pinconf_set()
From: Mario Limonciello <mario.limonciello@xxxxxxx>
commit 283c5ce7da0a676f46539094d40067ad17c4f294 upstream.
Debounce handling is done in two different entry points in the driver.
Unify this to make sure that it's always handled the same.
Tested-by: Jan Visser <starquake@xxxxxxxxxxxxxxxxxxx>
Signed-off-by: Mario Limonciello <mario.limonciello@xxxxxxx>
Link: https://lore.kernel.org/r/20230705133005.577-5-mario.limonciello@xxxxxxx
Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/pinctrl/pinctrl-amd.c | 21 +++++----------------
1 file changed, 5 insertions(+), 16 deletions(-)
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -115,16 +115,12 @@ static void amd_gpio_set_value(struct gp
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
-static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
- unsigned debounce)
+static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
+ unsigned int debounce)
{
u32 time;
u32 pin_reg;
int ret = 0;
- unsigned long flags;
- struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
-
- raw_spin_lock_irqsave(&gpio_dev->lock, flags);
/* Use special handling for Pin0 debounce */
if (offset == 0) {
@@ -183,7 +179,6 @@ static int amd_gpio_set_debounce(struct
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
}
writel(pin_reg, gpio_dev->base + offset * 4);
- raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
}
@@ -782,9 +777,8 @@ static int amd_pinconf_set(struct pinctr
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
- pin_reg &= ~DB_TMR_OUT_MASK;
- pin_reg |= arg & DB_TMR_OUT_MASK;
- break;
+ ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
+ goto out_unlock;
case PIN_CONFIG_BIAS_PULL_DOWN:
pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
@@ -811,6 +805,7 @@ static int amd_pinconf_set(struct pinctr
writel(pin_reg, gpio_dev->base + pin*4);
}
+out_unlock:
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
@@ -857,12 +852,6 @@ static int amd_gpio_set_config(struct gp
{
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
- u32 debounce = pinconf_to_config_argument(config);
-
- return amd_gpio_set_debounce(gc, pin, debounce);
- }
-
return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
}
Patches currently in stable-queue which might be from mario.limonciello@xxxxxxx are
queue-6.1/pinctrl-amd-detect-internal-gpio0-debounce-handling.patch
queue-6.1/pinctrl-amd-only-use-special-debounce-behavior-for-gpio-0.patch
queue-6.1/pinctrl-amd-adjust-debugfs-output.patch
queue-6.1/pinctrl-amd-revert-pinctrl-amd-disable-and-mask-interrupts-on-probe.patch
queue-6.1/pinctrl-amd-detect-and-mask-spurious-interrupts.patch
queue-6.1/pinctrl-amd-drop-pull-up-select-configuration.patch
queue-6.1/pinctrl-amd-fix-mistake-in-handling-clearing-pins-at-startup.patch
queue-6.1/pinctrl-amd-add-z-state-wake-control-bits.patch
queue-6.1/drm-amdgpu-sdma4-set-align-mask-to-255.patch
queue-6.1/pinctrl-amd-use-amd_pinconf_set-for-all-config-options.patch
queue-6.1/pinctrl-amd-unify-debounce-handling-into-amd_pinconf_set.patch
queue-6.1/drm-client-send-hotplug-event-after-registering-a-client.patch
queue-6.1/pinctrl-amd-add-fields-for-interrupt-status-and-wake-status.patch
