This is a note to let you know that I've just added the patch titled
irqchip/loongson-pch-pic: Fix initialization of HT vector register
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
irqchip-loongson-pch-pic-fix-initialization-of-ht-vector-register.patch
and it can be found in the queue-6.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From f679616565f1cf1a4acb245dbc0032dafcd40637 Mon Sep 17 00:00:00 2001
From: Jianmin Lv <lvjianmin@xxxxxxxxxxx>
Date: Wed, 14 Jun 2023 19:59:32 +0800
Subject: irqchip/loongson-pch-pic: Fix initialization of HT vector register
From: Jianmin Lv <lvjianmin@xxxxxxxxxxx>
commit f679616565f1cf1a4acb245dbc0032dafcd40637 upstream.
In an ACPI-based dual-bridge system, IRQ of each bridge's
PCH PIC sent to CPU is always a zero-based number, which
means that the IRQ on PCH PIC of each bridge is mapped into
vector range from 0 to 63 of upstream irqchip(e.g. EIOINTC).
EIOINTC N: [0 ... 63 | 64 ... 255]
-------- ----------
^ ^
| |
PCH PIC N |
PCH MSI N
For example, the IRQ vector number of sata controller on
PCH PIC of each bridge is 16, which is sent to upstream
irqchip of EIOINTC when an interrupt occurs, which will set
bit 16 of EIOINTC. Since hwirq of 16 on EIOINTC has been
mapped to a irq_desc for sata controller during hierarchy
irq allocation, the related mapped IRQ will be found through
irq_resolve_mapping() in the IRQ domain of EIOINTC.
So, the IRQ number set in HT vector register should be fixed
to be a zero-based number.
Cc: stable@xxxxxxxxxxxxxxx
Reviewed-by: Huacai Chen <chenhuacai@xxxxxxxxxxx>
Co-developed-by: liuyun <liuyun@xxxxxxxxxxx>
Signed-off-by: liuyun <liuyun@xxxxxxxxxxx>
Signed-off-by: Jianmin Lv <lvjianmin@xxxxxxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20230614115936.5950-2-lvjianmin@xxxxxxxxxxx
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/irqchip/irq-loongson-pch-pic.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
--- a/drivers/irqchip/irq-loongson-pch-pic.c
+++ b/drivers/irqchip/irq-loongson-pch-pic.c
@@ -350,14 +350,12 @@ static int __init acpi_cascade_irqdomain
int __init pch_pic_acpi_init(struct irq_domain *parent,
struct acpi_madt_bio_pic *acpi_pchpic)
{
- int ret, vec_base;
+ int ret;
struct fwnode_handle *domain_handle;
if (find_pch_pic(acpi_pchpic->gsi_base) >= 0)
return 0;
- vec_base = acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ;
-
domain_handle = irq_domain_alloc_fwnode(&acpi_pchpic->address);
if (!domain_handle) {
pr_err("Unable to allocate domain handle\n");
@@ -365,7 +363,7 @@ int __init pch_pic_acpi_init(struct irq_
}
ret = pch_pic_init(acpi_pchpic->address, acpi_pchpic->size,
- vec_base, parent, domain_handle, acpi_pchpic->gsi_base);
+ 0, parent, domain_handle, acpi_pchpic->gsi_base);
if (ret < 0) {
irq_domain_free_fwnode(domain_handle);
Patches currently in stable-queue which might be from lvjianmin@xxxxxxxxxxx are
queue-6.1/irqchip-loongson-pch-pic-fix-initialization-of-ht-vector-register.patch
queue-6.1/irqchip-loongson-pch-pic-fix-potential-incorrect-hwirq-assignment.patch
