This is a note to let you know that I've just added the patch titled
clk: qcom: dispcc-qcm2290: Fix GPLL0_OUT_DIV handling
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-qcom-dispcc-qcm2290-fix-gpll0_out_div-handling.patch
and it can be found in the queue-6.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit f0ab3f917f58eade5f247b76d51bd1c46be0d5d4
Author: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Date: Fri Apr 14 13:06:36 2023 +0200
clk: qcom: dispcc-qcm2290: Fix GPLL0_OUT_DIV handling
[ Upstream commit 63d56adf04b5795e54440dc5b7afddecb2966863 ]
GPLL0_OUT_DIV (.fw_name = "gcc_disp_gpll0_div_clk_src") was previously
made to reuse the same parent enum entry as GPLL0_OUT_MAIN
(.fw_name = "gcc_disp_gpll0_clk_src") in parent_map_2.
Resolve it by introducing its own entry in the parent enum and
correctly assigning it in disp_cc_parent_map_2[].
Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-2-bce7dd512fe4@xxxxxxxxxx
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 4a4993470852b..5cec98c4e8372 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -27,6 +27,7 @@ enum {
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
+ P_GPLL0_OUT_DIV,
P_GPLL0_OUT_MAIN,
P_SLEEP_CLK,
};
@@ -83,7 +84,7 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = {
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO_AO, 0 },
- { P_GPLL0_OUT_MAIN, 4 },
+ { P_GPLL0_OUT_DIV, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
@@ -152,8 +153,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO_AO, 1, 0, 0),
- F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
- F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
+ F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
{ }
};
