This is a note to let you know that I've just added the patch titled
arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz
to the 5.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-dts-mediatek-mt8192-fix-cpus-capacity-dmips-mh.patch
and it can be found in the queue-5.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit 1e92f250a335e565f7d510eeb2fa8881f5866846
Author: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
Date: Fri Jun 2 14:35:15 2023 -0400
arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz
[ Upstream commit a4366b5695c984b8a3fc8b31de9e758c8f6d1aed ]
The capacity-dmips-mhz parameter was miscalculated: this SoC runs
the first (Cortex-A55) cluster at a maximum of 2000MHz and the
second (Cortex-A76) cluster at a maximum of 2200MHz.
In order to calculate the right capacity-dmips-mhz, the following
test was performed:
1. CPUFREQ governor was set to 'performance' on both clusters
2. Ran dhrystone with 500000000 iterations for 10 times on each cluster
3. Calculated the mean result for each cluster
4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz
5. Scaled results to 1024:
result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024
The mean results for this SoC are:
Cluster 0 (LITTLE): 12016411 Dhry/s
Cluster 1 (BIG): 31702034 Dhry/s
The calculated scaled results are:
Cluster 0: 426.953226899238 (rounded to 427)
Cluster 1: 1024
Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile")
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
Link: https://lore.kernel.org/r/20230602183515.3778780-1-nfraprado@xxxxxxxxxxxxx
Signed-off-by: Matthias Brugger <matthias.bgg@xxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 19ba781729722..72f444405ebfe 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -42,7 +42,7 @@ cpu0: cpu@0 {
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
- capacity-dmips-mhz = <530>;
+ capacity-dmips-mhz = <427>;
};
cpu1: cpu@100 {
@@ -54,7 +54,7 @@ cpu1: cpu@100 {
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
- capacity-dmips-mhz = <530>;
+ capacity-dmips-mhz = <427>;
};
cpu2: cpu@200 {
@@ -66,7 +66,7 @@ cpu2: cpu@200 {
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
- capacity-dmips-mhz = <530>;
+ capacity-dmips-mhz = <427>;
};
cpu3: cpu@300 {
@@ -78,7 +78,7 @@ cpu3: cpu@300 {
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
- capacity-dmips-mhz = <530>;
+ capacity-dmips-mhz = <427>;
};
cpu4: cpu@400 {
