Patch "arm64: dts: imx8mn-beacon: Fix SPI CS pinmux" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64: dts: imx8mn-beacon: Fix SPI CS pinmux

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-imx8mn-beacon-fix-spi-cs-pinmux.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 6ebe6a9e9f03619917cb381db8b6a9ece71e04c8
Author: Adam Ford <aford173@xxxxxxxxx>
Date:   Sun May 28 06:22:54 2023 -0500

    arm64: dts: imx8mn-beacon: Fix SPI CS pinmux
    
    [ Upstream commit 9bf2e534313fcf420367668cc1f30e10469901dc ]
    
    The final production baseboard had a different chip select than
    earlier prototype boards.  When the newer board was released,
    the SPI stopped working because the wrong pin was used in the device
    tree and conflicted with the UART RTS. Fix the pinmux for
    production boards.
    
    Fixes: 36ca3c8ccb53 ("arm64: dts: imx: Add Beacon i.MX8M Nano development kit")
    Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
    Signed-off-by: Shawn Guo <shawnguo@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
index 9e82069c941fa..5a1f7c30afe57 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
@@ -81,7 +81,7 @@ sound {
 &ecspi2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_espi2>;
-	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
 	eeprom@0 {
@@ -202,7 +202,7 @@ pinctrl_espi2: espi2grp {
 			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
 			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
 			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
-			MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41
+			MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x41
 		>;
 	};
 



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