Patch "drm/amdgpu/gfx11: update gpu_clock_counter logic" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amdgpu/gfx11: update gpu_clock_counter logic

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amdgpu-gfx11-update-gpu_clock_counter-logic.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.


>From d5aa417808cf14c052ca042920b3c6b9f1dc6aa4 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Mon, 10 Apr 2023 12:02:29 -0400
Subject: drm/amdgpu/gfx11: update gpu_clock_counter logic

From: Alex Deucher <alexander.deucher@xxxxxxx>

commit d5aa417808cf14c052ca042920b3c6b9f1dc6aa4 upstream.

This code was written prior to previous updates to this
logic for other chips.  The RSC registers are part of
SMUIO which is an always on block so there is no need
to disable gfxoff.  Additionally add the carryover and
preemption checks.

v2: rebase

Reviewed-by: Hawking Zhang <Hawking.Zhang@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx # 6.1.y: 5591a051b86b: drm/amdgpu: refine get gpu clock counter method
Cc: stable@xxxxxxxxxxxxxxx # 6.2.y: 5591a051b86b: drm/amdgpu: refine get gpu clock counter method
Cc: stable@xxxxxxxxxxxxxxx # 6.3.y: 5591a051b86b: drm/amdgpu: refine get gpu clock counter method
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c |   11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4643,24 +4643,27 @@ static uint64_t gfx_v11_0_get_gpu_clock_
 	uint64_t clock;
 	uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;
 
-	amdgpu_gfx_off_ctrl(adev, false);
-	mutex_lock(&adev->gfx.gpu_clock_mutex);
 	if (amdgpu_sriov_vf(adev)) {
+		amdgpu_gfx_off_ctrl(adev, false);
+		mutex_lock(&adev->gfx.gpu_clock_mutex);
 		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
 		clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
 		clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
 		if (clock_counter_hi_pre != clock_counter_hi_after)
 			clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
+		mutex_unlock(&adev->gfx.gpu_clock_mutex);
+		amdgpu_gfx_off_ctrl(adev, true);
 	} else {
+		preempt_disable();
 		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
 		clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
 		clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
 		if (clock_counter_hi_pre != clock_counter_hi_after)
 			clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
+		preempt_enable();
 	}
 	clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);
-	mutex_unlock(&adev->gfx.gpu_clock_mutex);
-	amdgpu_gfx_off_ctrl(adev, true);
+
 	return clock;
 }
 


Patches currently in stable-queue which might be from alexander.deucher@xxxxxxx are

queue-6.1/drm-amdgpu-gfx11-update-gpu_clock_counter-logic.patch
queue-6.1/drm-amdgpu-gfx10-disable-gfxoff-before-disabling-powergating.patch
queue-6.1/drm-amd-pm-fix-possible-power-mode-mismatch-between-driver-and-pmfw.patch
queue-6.1/drm-amdgpu-refine-get-gpu-clock-counter-method.patch
queue-6.1/drm-amd-display-use-dc_log_dc-in-the-trasform-pixel-.patch
queue-6.1/drm-amdgpu-gfx11-adjust-gfxoff-before-powergating-on-gfx11-as-well.patch
queue-6.1/drm-amd-display-enable-hostvm-based-on-riommu-active.patch
queue-6.1/drm-amd-display-populate-subvp-cmd-info-only-for-the.patch
queue-6.1/drm-amd-display-correct-dml-calculation-to-follow-hw.patch
queue-6.1/drm-amd-fix-an-out-of-bounds-error-in-bios-parser.patch
queue-6.1/drm-amdgpu-fix-sdma-v4-sw-fini-error.patch
queue-6.1/drm-amd-display-correct-dml-calculation-to-align-hw-.patch
queue-6.1/drm-amd-display-fixed-dcn30-underflow-issue.patch
queue-6.1/drm-amdgpu-gmc11-implement-get_vbios_fb_size.patch
queue-6.1/drm-amdgpu-drop-gfx_v11_0_cp_ecc_error_irq_funcs.patch



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