Patch "net: stmmac: Initialize MAC_ONEUS_TIC_COUNTER register" has been added to the 6.3-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    net: stmmac: Initialize MAC_ONEUS_TIC_COUNTER register

to the 6.3-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     net-stmmac-initialize-mac_oneus_tic_counter-register.patch
and it can be found in the queue-6.3 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit af422c3009ce35808c0179babb34f3c02f12b391
Author: Marek Vasut <marex@xxxxxxx>
Date:   Sun May 7 01:58:45 2023 +0200

    net: stmmac: Initialize MAC_ONEUS_TIC_COUNTER register
    
    [ Upstream commit 8efbdbfa99381a017dd2c0f6375a7d80a8118b74 ]
    
    Initialize MAC_ONEUS_TIC_COUNTER register with correct value derived
    from CSR clock, otherwise EEE is unstable on at least NXP i.MX8M Plus
    and Micrel KSZ9131RNX PHY, to the point where not even ARP request can
    be sent out.
    
    i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/2021
    11.7.6.1.34 One-microsecond Reference Timer (MAC_ONEUS_TIC_COUNTER)
    defines this register as:
    "
    This register controls the generation of the Reference time (1 microsecond
    tic) for all the LPI timers. This timer has to be programmed by the software
    initially.
    ...
    The application must program this counter so that the number of clock cycles
    of CSR clock is 1us. (Subtract 1 from the value before programming).
    For example if the CSR clock is 100MHz then this field needs to be programmed
    to value 100 - 1 = 99 (which is 0x63).
    This is required to generate the 1US events that are used to update some of
    the EEE related counters.
    "
    
    The reset value is 0x63 on i.MX8M Plus, which means expected CSR clock are
    100 MHz. However, the i.MX8M Plus "enet_qos_root_clk" are 266 MHz instead,
    which means the LPI timers reach their count much sooner on this platform.
    
    This is visible using a scope by monitoring e.g. exit from LPI mode on TX_CTL
    line from MAC to PHY. This should take 30us per STMMAC_DEFAULT_TWT_LS setting,
    during which the TX_CTL line transitions from tristate to low, and 30 us later
    from low to high. On i.MX8M Plus, this transition takes 11 us, which matches
    the 30us * 100/266 formula for misconfigured MAC_ONEUS_TIC_COUNTER register.
    
    Configure MAC_ONEUS_TIC_COUNTER based on CSR clock, so that the LPI timers
    have correct 1us reference. This then fixes EEE on i.MX8M Plus with Micrel
    KSZ9131RNX PHY.
    
    Fixes: 477286b53f55 ("stmmac: add GMAC4 core support")
    Signed-off-by: Marek Vasut <marex@xxxxxxx>
    Tested-by: Harald Seiler <hws@xxxxxxx>
    Reviewed-by: Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx>
    Tested-by: Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx> # Toradex Verdin iMX8MP
    Reviewed-by: Jesse Brandeburg <jesse.brandeburg@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20230506235845.246105-1-marex@xxxxxxx
    Signed-off-by: Jakub Kicinski <kuba@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index ccd49346d3b30..a70b0d8a622d6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -181,6 +181,7 @@ enum power_event {
 #define GMAC4_LPI_CTRL_STATUS	0xd0
 #define GMAC4_LPI_TIMER_CTRL	0xd4
 #define GMAC4_LPI_ENTRY_TIMER	0xd8
+#define GMAC4_MAC_ONEUS_TIC_COUNTER	0xdc
 
 /* LPI control and status defines */
 #define GMAC4_LPI_CTRL_STATUS_LPITCSE	BIT(21)	/* LPI Tx Clock Stop Enable */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index 36251ec2589c9..24d6ec06732d9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -25,6 +25,7 @@ static void dwmac4_core_init(struct mac_device_info *hw,
 	struct stmmac_priv *priv = netdev_priv(dev);
 	void __iomem *ioaddr = hw->pcsr;
 	u32 value = readl(ioaddr + GMAC_CONFIG);
+	u32 clk_rate;
 
 	value |= GMAC_CORE_INIT;
 
@@ -47,6 +48,10 @@ static void dwmac4_core_init(struct mac_device_info *hw,
 
 	writel(value, ioaddr + GMAC_CONFIG);
 
+	/* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1 */
+	clk_rate = clk_get_rate(priv->plat->stmmac_clk);
+	writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);
+
 	/* Enable GMAC interrupts */
 	value = GMAC_INT_DEFAULT_ENABLE;