Patch "drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203" has been added to the 6.3-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203

to the 6.3-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-i915-mtl-add-workarounds-wa_14017066071-and-wa_1.patch
and it can be found in the queue-6.3 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit ac4ebce04733b7200231b2c1101936568d497736
Author: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
Date:   Wed Mar 29 18:23:35 2023 -0300

    drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203
    
    [ Upstream commit 5fba65efa7cfb8cef227a2c555deb10327a5e27b ]
    
    Both workarounds require the same implementation and apply to MTL P and
    M from stepping A0 to B0 (exclusive).
    
    v2:
      - Remove unrelated brace removal. (Matt)
    
    Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
    Signed-off-by: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
    Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
    Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
    Link: https://patchwork.freedesktop.org/patch/msgid/20230329212336.106161-2-gustavo.sousa@xxxxxxxxx
    Stable-dep-of: 81900e3a3775 ("drm/i915: disable sampler indirect state in bindless heap")
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index be0f6e305c881..15b8636853ff0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1145,6 +1145,7 @@
 #define   ENABLE_SMALLPL			REG_BIT(15)
 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
+#define   MTL_DISABLE_SAMPLER_SC_OOO		REG_BIT(3)
 
 #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 485c5cc5d0f96..bfdffb6a013ce 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -3015,6 +3015,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 
 	add_render_compute_tuning_settings(i915, wal);
 
+	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+		/*
+		 * Wa_14017066071
+		 * Wa_14017654203
+		 */
+		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+				 MTL_DISABLE_SAMPLER_SC_OOO);
+
 	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||



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