This is a note to let you know that I've just added the patch titled
drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes
to the 6.3-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-amd-display-enforce-60us-prefetch-for-200mhz-dcfclk-modes.patch
and it can be found in the queue-6.3 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From b504f99ccaa64da364443431e388ecf30b604e38 Mon Sep 17 00:00:00 2001
From: Alvin Lee <Alvin.Lee2@xxxxxxx>
Date: Thu, 27 Apr 2023 15:10:13 -0400
Subject: drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes
From: Alvin Lee <Alvin.Lee2@xxxxxxx>
commit b504f99ccaa64da364443431e388ecf30b604e38 upstream.
[Description]
- Due to bandwidth / arbitration issues at 200Mhz DCFCLK,
we want to enforce minimum 60us of prefetch to avoid
intermittent underflow issues
- Since 60us prefetch is already enforced for UCLK DPM0,
and many DCFCLK's > 200Mhz are mapped to UCLK DPM1, in
theory there should not be any UCLK DPM regressions by
enforcing greater prefetch
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@xxxxxxx>
Reviewed-by: Jun Lei <Jun.Lei@xxxxxxx>
Cc: Mario Limonciello <mario.limonciello@xxxxxxx>
Cc: Alex Deucher <alexander.deucher@xxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Acked-by: Alex Hung <alex.hung@xxxxxxx>
Signed-off-by: Alvin Lee <Alvin.Lee2@xxxxxxx>
Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 5 +++--
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h | 1 +
2 files changed, 4 insertions(+), 2 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -810,7 +810,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleep
v->SwathHeightY[k],
v->SwathHeightC[k],
TWait,
- v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ?
+ (v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||
+ v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= MIN_DCFCLK_FREQ_MHZ) ?
mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
/* Output */
&v->DSTXAfterScaler[k],
@@ -3309,7 +3310,7 @@ void dml32_ModeSupportAndSystemConfigura
v->swath_width_chroma_ub_this_state[k],
v->SwathHeightYThisState[k],
v->SwathHeightCThisState[k], v->TWait,
- v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ?
+ (v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= MIN_DCFCLK_FREQ_MHZ) ?
mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
/* Output */
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
@@ -53,6 +53,7 @@
#define BPP_BLENDED_PIPE 0xffffffff
#define MEM_STROBE_FREQ_MHZ 1600
+#define MIN_DCFCLK_FREQ_MHZ 200
#define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0
struct display_mode_lib;
Patches currently in stable-queue which might be from Alvin.Lee2@xxxxxxx are
queue-6.3/drm-amd-display-filter-out-invalid-bits-in-pipe_fuses.patch
queue-6.3/drm-amd-display-enforce-60us-prefetch-for-200mhz-dcfclk-modes.patch
