This is a note to let you know that I've just added the patch titled
arm64: dts: qcom: ipq8074: Fix the PCI I/O port range
to the 5.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-dts-qcom-ipq8074-fix-the-pci-i-o-port-range.patch
and it can be found in the queue-5.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit 73a443026d768368507ea688994ed5ba37adfdb3
Author: Manivannan Sadhasivam <mani@xxxxxxxxxx>
Date: Tue Feb 28 22:17:41 2023 +0530
arm64: dts: qcom: ipq8074: Fix the PCI I/O port range
[ Upstream commit e49eafefe5ab325e38dd074f2005076ffc271e54 ]
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses
(0x10200000, 0x20200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses and align
them in a single line.
Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
Reported-by: Arnd Bergmann <arnd@xxxxxxxx>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@xxxxxxxxxxxxxxxx/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Reviewed-by: Arnd Bergmann <arnd@xxxxxxxx>
Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20230228164752.55682-6-manivannan.sadhasivam@xxxxxxxxxx
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index e191a7bc532be..f85fcc7c8676b 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -609,10 +609,8 @@ pcie1: pci@10000000 {
phys = <&pcie_phy1>;
phy-names = "pciephy";
- ranges = <0x81000000 0 0x10200000 0x10200000
- 0 0x10000>, /* downstream I/O */
- <0x82000000 0 0x10220000 0x10220000
- 0 0xfde0000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
+ <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -673,10 +671,8 @@ pcie0: pci@20000000 {
phys = <&pcie_phy0>;
phy-names = "pciephy";
- ranges = <0x81000000 0 0x20200000 0x20200000
- 0 0x10000>, /* downstream I/O */
- <0x82000000 0 0x20220000 0x20220000
- 0 0xfde0000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
+ <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
