This is a note to let you know that I've just added the patch titled
arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588s
to the 6.3-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-dts-rockchip-assign-pll_ppll-clock-rate-to-1.1.patch
and it can be found in the queue-6.3 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit a149a8f2389216a8cfd8b54d787b47484b7421db
Author: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx>
Date: Sun Apr 2 12:50:51 2023 +0300
arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588s
[ Upstream commit b46a22dea7530cf530a45c6b84c03300083b813d ]
The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz
instead of 1.1 GHz. Fix it.
Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Reported-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx>
Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@xxxxxxxxxxxxx
Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index a506948b5572b..f4eae4dde1751 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -423,7 +423,7 @@ cru: clock-controller@fd7c0000 {
<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
<&cru CLK_GPU>;
assigned-clock-rates =
- <100000000>, <786432000>,
+ <1100000000>, <786432000>,
<850000000>, <1188000000>,
<702000000>,
<400000000>, <500000000>,
