Patch "drm/amd/display: limit timing for single dimm memory" has been added to the 6.1-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    drm/amd/display: limit timing for single dimm memory

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-limit-timing-for-single-dimm-memory.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit f9bd1f0f032abf5d2b6b2b151a00be0d73fd80b3
Author: Daniel Miess <Daniel.Miess@xxxxxxx>
Date:   Tue Apr 4 14:04:11 2023 -0400

    drm/amd/display: limit timing for single dimm memory
    
    [ Upstream commit 1e994cc0956b8dabd1b1fef315bbd722733b8aa8 ]
    
    [Why]
    1. It could hit bandwidth limitdation under single dimm
    memory when connecting 8K external monitor.
    2. IsSupportedVidPn got validation failed with
    2K240Hz eDP + 8K24Hz external monitor.
    3. It's better to filter out such combination in
    EnumVidPnCofuncModality
    4. For short term, filter out in dc bandwidth validation.
    
    [How]
    Force 2K@240Hz+8K@24Hz timing validation false in dc.
    
    Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@xxxxxxx>
    Acked-by: Qingqing Zhuo <qingqing.zhuo@xxxxxxx>
    Signed-off-by: Daniel Miess <Daniel.Miess@xxxxxxx>
    Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Cc: stable@xxxxxxxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 2f9c6d64b98bc..ffaa4e5b3fca0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1689,6 +1689,23 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi
 	*panel_config = panel_config_defaults;
 }
 
+static bool filter_modes_for_single_channel_workaround(struct dc *dc,
+		struct dc_state *context)
+{
+	// Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR
+	if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) {
+		int total_phy_pix_clk = 0;
+
+		for (int i = 0; i < context->stream_count; i++)
+			if (context->res_ctx.pipe_ctx[i].stream)
+				total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
+
+		if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
+			return true;
+	}
+	return false;
+}
+
 bool dcn314_validate_bandwidth(struct dc *dc,
 		struct dc_state *context,
 		bool fast_validate)
@@ -1704,6 +1721,9 @@ bool dcn314_validate_bandwidth(struct dc *dc,
 
 	BW_VAL_TRACE_COUNT();
 
+	if (filter_modes_for_single_channel_workaround(dc, context))
+		goto validate_fail;
+
 	DC_FP_START();
 	// do not support self refresh only
 	out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);