This is a note to let you know that I've just added the patch titled
KVM: x86: Inject #GP on x2APIC WRMSR that sets reserved bits 63:32
to the 5.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
kvm-x86-inject-gp-on-x2apic-wrmsr-that-sets-reserved-bits-63-32.patch
and it can be found in the queue-5.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From ab52be1b310bcb39e6745d34a8f0e8475d67381a Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@xxxxxxxxxx>
Date: Sat, 7 Jan 2023 01:10:21 +0000
Subject: KVM: x86: Inject #GP on x2APIC WRMSR that sets reserved bits 63:32
From: Sean Christopherson <seanjc@xxxxxxxxxx>
commit ab52be1b310bcb39e6745d34a8f0e8475d67381a upstream.
Reject attempts to set bits 63:32 for 32-bit x2APIC registers, i.e. all
x2APIC registers except ICR. Per Intel's SDM:
Non-zero writes (by WRMSR instruction) to reserved bits to these
registers will raise a general protection fault exception
Opportunistically fix a typo in a nearby comment.
Reported-by: Marc Orr <marcorr@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Reviewed-by: Maxim Levitsky <mlevitsk@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20230107011025.565472-3-seanjc@xxxxxxxxxx
Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/x86/kvm/lapic.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2802,6 +2802,10 @@ int kvm_x2apic_msr_write(struct kvm_vcpu
/* if this is ICR write vector before command */
if (reg == APIC_ICR)
kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
+ else if (data >> 32)
+ /* Bits 63:32 are reserved in all other registers. */
+ return 1;
+
return kvm_lapic_reg_write(apic, reg, (u32)data);
}
@@ -2836,6 +2840,10 @@ int kvm_hv_vapic_msr_write(struct kvm_vc
/* if this is ICR write vector before command */
if (reg == APIC_ICR)
kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
+ else if (data >> 32)
+ /* Bits 63:32 are reserved in all other registers. */
+ return 1;
+
return kvm_lapic_reg_write(apic, reg, (u32)data);
}
Patches currently in stable-queue which might be from seanjc@xxxxxxxxxx are
queue-5.15/kvm-vmx-move-preemption-timer-hrtimer-dance-to-common-x86.patch
queue-5.15/kvm-x86-purge-highest-isr-cache-when-updating-apicv-state.patch
queue-5.15/kvm-x86-inject-gp-on-x2apic-wrmsr-that-sets-reserved-bits-63-32.patch
