Patch "PCI: dwc: Fix PORT_LINK_CONTROL update when CDM check enabled" has been added to the 6.1-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    PCI: dwc: Fix PORT_LINK_CONTROL update when CDM check enabled

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     pci-dwc-fix-port_link_control-update-when-cdm-check-.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 4866df8075f3ce36181209d8170d9e605315a6f6
Author: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Date:   Fri Mar 10 21:34:58 2023 +0900

    PCI: dwc: Fix PORT_LINK_CONTROL update when CDM check enabled
    
    [ Upstream commit cdce67099117ece371582f706c6eff7d3a65326d ]
    
    If CDM_CHECK is enabled (by the DT "snps,enable-cdm-check" property), 'val'
    is overwritten by PCIE_PL_CHK_REG_CONTROL_STATUS initialization.  Commit
    ec7b952f453c ("PCI: dwc: Always enable CDM check if "snps,enable-cdm-check"
    exists") did not account for further usage of 'val', so we wrote improper
    values to PCIE_PORT_LINK_CONTROL when the CDM check is enabled.
    
    Move the PCIE_PORT_LINK_CONTROL update to be completely after the
    PCIE_PL_CHK_REG_CONTROL_STATUS register initialization.
    
    [bhelgaas: commit log adapted from Serge's version]
    Fixes: ec7b952f453c ("PCI: dwc: Always enable CDM check if "snps,enable-cdm-check" exists")
    Link: https://lore.kernel.org/r/20230310123510.675685-2-yoshihiro.shimoda.uh@xxxxxxxxxxx
    Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
    Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
    Reviewed-by: Serge Semin <fancer.lancer@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 9e4d96e5a3f5a..575834cae3b9e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -645,11 +645,6 @@ void dw_pcie_setup(struct dw_pcie *pci)
 		dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
 	}
 
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
-	val &= ~PORT_LINK_FAST_LINK_MODE;
-	val |= PORT_LINK_DLL_LINK_EN;
-	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
-
 	if (of_property_read_bool(np, "snps,enable-cdm-check")) {
 		val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
 		val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
@@ -657,6 +652,11 @@ void dw_pcie_setup(struct dw_pcie *pci)
 		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
 	}
 
+	val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
+	val &= ~PORT_LINK_FAST_LINK_MODE;
+	val |= PORT_LINK_DLL_LINK_EN;
+	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
+
 	of_property_read_u32(np, "num-lanes", &pci->num_lanes);
 	if (!pci->num_lanes) {
 		dev_dbg(pci->dev, "Using h/w default number of lanes\n");