Patch "ACPI: x86: utils: Add Cezanne to the list for forcing StorageD3Enable" has been added to the 6.2-stable tree

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This is a note to let you know that I've just added the patch titled

    ACPI: x86: utils: Add Cezanne to the list for forcing StorageD3Enable

to the 6.2-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     acpi-x86-utils-add-cezanne-to-the-list-for-forcing-s.patch
and it can be found in the queue-6.2 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 55050812967c802e5ddd454129e2d056ed450b33
Author: Mario Limonciello <mario.limonciello@xxxxxxx>
Date:   Tue Feb 28 16:11:28 2023 -0600

    ACPI: x86: utils: Add Cezanne to the list for forcing StorageD3Enable
    
    [ Upstream commit e2a56364485e7789e7b8f342637c7f3a219f7ede ]
    
    commit 018d6711c26e4 ("ACPI: x86: Add a quirk for Dell Inspiron 14 2-in-1
    for StorageD3Enable") introduced a quirk to allow a system with ambiguous
    use of _ADR 0 to force StorageD3Enable.
    
    It was reported that several more Dell systems suffered the same symptoms.
    As the list is continuing to grow but these are all Cezanne systems,
    instead add Cezanne to the CPU list to apply the StorageD3Enable property
    and remove the whole list.
    
    It was also reported that an HP system only has StorageD3Enable on the ACPI
    device for the first NVME disk, not the second.
    
    Link: https://bugzilla.kernel.org/show_bug.cgi?id=217003
    Link: https://bugzilla.kernel.org/show_bug.cgi?id=216773
    Reported-by: David Alvarez Lombardi <dqalombardi@xxxxxxxxx>
    Reported-by: dbilios@xxxxxxxx
    Reported-and-tested-by: Elvis Angelaccio <elvis.angelaccio@xxxxxxx>
    Tested-by: victor.bonnelle@xxxxxxxxx
    Tested-by: hurricanepootis@xxxxxxxxxxxxxx
    Signed-off-by: Mario Limonciello <mario.limonciello@xxxxxxx>
    Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/acpi/x86/utils.c b/drivers/acpi/x86/utils.c
index 4e816bb402f68..e45285d4e62a4 100644
--- a/drivers/acpi/x86/utils.c
+++ b/drivers/acpi/x86/utils.c
@@ -200,39 +200,28 @@ bool acpi_device_override_status(struct acpi_device *adev, unsigned long long *s
  * a hardcoded allowlist for D3 support, which was used for these platforms.
  *
  * This allows quirking on Linux in a similar fashion.
+ *
+ * Cezanne systems shouldn't *normally* need this as the BIOS includes
+ * StorageD3Enable.  But for two reasons we have added it.
+ * 1) The BIOS on a number of Dell systems have ambiguity
+ *    between the same value used for _ADR on ACPI nodes GPP1.DEV0 and GPP1.NVME.
+ *    GPP1.NVME is needed to get StorageD3Enable node set properly.
+ *    https://bugzilla.kernel.org/show_bug.cgi?id=216440
+ *    https://bugzilla.kernel.org/show_bug.cgi?id=216773
+ *    https://bugzilla.kernel.org/show_bug.cgi?id=217003
+ * 2) On at least one HP system StorageD3Enable is missing on the second NVME
+      disk in the system.
  */
 static const struct x86_cpu_id storage_d3_cpu_ids[] = {
 	X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL),	/* Renoir */
 	X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104, NULL),	/* Lucienne */
-	{}
-};
-
-static const struct dmi_system_id force_storage_d3_dmi[] = {
-	{
-		/*
-		 * _ADR is ambiguous between GPP1.DEV0 and GPP1.NVME
-		 * but .NVME is needed to get StorageD3Enable node
-		 * https://bugzilla.kernel.org/show_bug.cgi?id=216440
-		 */
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-			DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14 7425 2-in-1"),
-		}
-	},
-	{
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-			DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 16 5625"),
-		}
-	},
+	X86_MATCH_VENDOR_FAM_MODEL(AMD, 25, 80, NULL),	/* Cezanne */
 	{}
 };
 
 bool force_storage_d3(void)
 {
-	const struct dmi_system_id *dmi_id = dmi_first_match(force_storage_d3_dmi);
-
-	return dmi_id || x86_match_cpu(storage_d3_cpu_ids);
+	return x86_match_cpu(storage_d3_cpu_ids);
 }
 
 /*



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