This is a note to let you know that I've just added the patch titled
drm/amd/display: Do not set DRR on pipe Commit
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-amd-display-do-not-set-drr-on-pipe-commit.patch
and it can be found in the queue-6.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 56574f89dbd84004c3fd6485bcaafb5aa9b8be14 Mon Sep 17 00:00:00 2001
From: Wesley Chalmers <Wesley.Chalmers@xxxxxxx>
Date: Thu, 3 Nov 2022 22:29:31 -0400
Subject: drm/amd/display: Do not set DRR on pipe Commit
From: Wesley Chalmers <Wesley.Chalmers@xxxxxxx>
commit 56574f89dbd84004c3fd6485bcaafb5aa9b8be14 upstream.
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
Cc: stable@xxxxxxxxxxxxxxx
Cc: Mario Limonciello <mario.limonciello@xxxxxxx>
Reviewed-by: Jun Lei <Jun.Lei@xxxxxxx>
Acked-by: Qingqing Zhuo <qingqing.zhuo@xxxxxxx>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@xxxxxxx>
Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 3 ---
1 file changed, 3 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -992,8 +992,5 @@ void dcn30_prepare_bandwidth(struct dc *
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
dcn20_prepare_bandwidth(dc, context);
-
- dc_dmub_srv_p_state_delegate(dc,
- context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching, context);
}
Patches currently in stable-queue which might be from Wesley.Chalmers@xxxxxxx are
queue-6.1/drm-amd-display-do-not-set-drr-on-pipe-commit.patch
