Patch "riscv: Add header include guards to insn.h" has been added to the 6.2-stable tree

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This is a note to let you know that I've just added the patch titled

    riscv: Add header include guards to insn.h

to the 6.2-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     riscv-add-header-include-guards-to-insn.h.patch
and it can be found in the queue-6.2 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 0dd5e14fe466a7093b041ca66d410c82dec464a8
Author: Liao Chang <liaochang1@xxxxxxxxxx>
Date:   Sun Jan 29 17:42:42 2023 +0800

    riscv: Add header include guards to insn.h
    
    [ Upstream commit 8ac6e619d9d51b3eb5bae817db8aa94e780a0db4 ]
    
    Add header include guards to insn.h to prevent repeating declaration of
    any identifiers in insn.h.
    
    Fixes: edde5584c7ab ("riscv: Add SW single-step support for KDB")
    Signed-off-by: Liao Chang <liaochang1@xxxxxxxxxx>
    Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
    Fixes: c9c1af3f186a ("RISC-V: rename parse_asm.h to insn.h")
    Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20230129094242.282620-1-liaochang1@xxxxxxxxxx
    Cc: stable@xxxxxxxxxxxxxxx
    Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/riscv/include/asm/parse_asm.h b/arch/riscv/include/asm/parse_asm.h
index f36368de839f5..3cd00332d70f5 100644
--- a/arch/riscv/include/asm/parse_asm.h
+++ b/arch/riscv/include/asm/parse_asm.h
@@ -3,6 +3,9 @@
  * Copyright (C) 2020 SiFive
  */
 
+#ifndef _ASM_RISCV_INSN_H
+#define _ASM_RISCV_INSN_H
+
 #include <linux/bits.h>
 
 /* The bit field of immediate value in I-type instruction */
@@ -217,3 +220,5 @@ static inline bool is_ ## INSN_NAME ## _insn(long insn) \
 	(RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \
 	(RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \
 	(RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
+
+#endif /* _ASM_RISCV_INSN_H */



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