This is a note to let you know that I've just added the patch titled
mtd: spi-nor: spansion: Consider reserved bits in CFR5 register
to the 5.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mtd-spi-nor-spansion-consider-reserved-bits-in-cfr5-register.patch
and it can be found in the queue-5.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 3f592a869f87723314f0cb1ac232bd3bf8245be8 Mon Sep 17 00:00:00 2001
From: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx>
Date: Tue, 10 Jan 2023 18:47:02 +0200
Subject: mtd: spi-nor: spansion: Consider reserved bits in CFR5 register
From: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx>
commit 3f592a869f87723314f0cb1ac232bd3bf8245be8 upstream.
CFR5[6] is reserved bit and must be always 1. Set it to comply with flash
requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_{EN, DS}
definition, stop using magic numbers and describe the missing bit fields
in CFR5 register. This is useful for both readability and future possible
addition of Octal STR mode support.
Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash")
Cc: stable@xxxxxxxxxxxxxxx
Reported-by: Takahiro Kuwano <Takahiro.Kuwano@xxxxxxxxxxxx>
Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx>
Reviewed-by: Dhruva Gole <d-gole@xxxxxx>
Reviewed-by: Pratyush Yadav <ptyadav@xxxxxxxxx>
Tested-by: Dhruva Gole <d-gole@xxxxxx>
Link: https://lore.kernel.org/linux-mtd/20230110164703.83413-1-tudor.ambarus@xxxxxxxxxx
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/mtd/spi-nor/spansion.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -15,8 +15,13 @@
#define SPINOR_REG_CYPRESS_CFR3V 0x00800004
#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */
#define SPINOR_REG_CYPRESS_CFR5V 0x00800006
-#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3
-#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0
+#define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6)
+#define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1)
+#define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0)
+#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \
+ (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \
+ SPINOR_REG_CYPRESS_CFR5_OPI)
+#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6
#define SPINOR_OP_CYPRESS_RD_FAST 0xee
/**
Patches currently in stable-queue which might be from tudor.ambarus@xxxxxxxxxx are
queue-5.15/mtd-spi-nor-fix-shift-out-of-bounds-in-spi_nor_set_erase_type.patch
queue-5.15/mtd-spi-nor-sfdp-fix-index-value-for-sccr-dwords.patch
queue-5.15/mtd-spi-nor-spansion-consider-reserved-bits-in-cfr5-register.patch
